Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 2-14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. (US 20190027493 A1) hereafter referred to as Kimura in view of Yun et al. (US 20200091176 A1) hereafter referred to as Yun
In regard to claim 1 Kimura teaches a semiconductor device [see Fig. 14B], comprising:
a gate structure [“insulators 101A to 101C” “conductors 132A and 132B”] including conductive layers and insulating layers that are alternately stacked with each other;
a channel layer [“semiconductor 151”] extending along a sidewall of the gate structure in a direction in which the conductive layers and the insulating layers are stacked;
a tunnel insulating [“insulator 104 is preferably thinner than the insulator 102. When the insulator 104 is thinner than the insulator 102, charge can be moved by the tunnel effect from the semiconductor 151 (described later) to the insulator 111 through the insulator 104”] layer located between the gate structure and the channel layer;
blocking patterns [“insulator 102 functions as a gate insulating film”] located between the tunnel insulating layer and the conductive layers;
memory patterns [“For the insulator 111, silicon nitride or silicon nitride oxide is preferably used” “charge can be moved by the tunnel effect from the semiconductor 151 (described later) to the insulator 111 through the insulator 104”] located between the tunnel insulating layer and the blocking patterns; and
but does not teach
isolation layers located between the tunnel insulating and the insulating layers, the isolation layers protruding farther toward the tunnel insulating layer than the memory patterns and the blocking patterns,
wherein an interface is formed between each of the isolation layers and the tunnel insulating layer, the interface being convexly curved toward the tunnel insulating layer.
See Yun teaches see Fig. 4 that “charge trap patterns 130P” is cut into sections i.e. each “word line WL” faces it’s unique “charge trap patterns 130P” thus leakage between the bits is reduced, see Fig. 11C, Fig. 11G this is achieved by “Referring to FIG. 11F, each of the plurality of first air-gap portions AG1 exposing the sacrificial oxide film 122 is formed between the first insulating film 110A and the third insulating film 110C from among the plurality of insulating films 110 by removing the plurality of second insulating films 110B (see FIG. 11E) through the word line cut region WLC. Isotropic etching may be performed to remove the plurality of second insulating films 110B” “Referring to FIG. 11G, the plurality of sacrificial oxide films 122 are removed by using isotropic etching through the word line cut region WLC and the plurality of first air-gap portions AG1, the charge trap film 130 are divided into the plurality of charge trap patterns 130P by isotropically etching the charge trap film 130 that is exposed, and the plurality of second air-gap portions AG2 located between the plurality of charge trap patterns 130P are formed”, see refilling with insulation “In a process for forming the insulating plugs 164, an insulating material may be deposited on an inner side wall of the word line cut region WLC” i.e. in Yun AG2 is the insulation i.e. air , see also Figs. 16E-16H see “Referring to FIG. 16F, the plurality of first sacrificial films 310 are removed by using isotropic etching through the word line cut region WLC”, then “Referring to FIG. 16G, a plurality of expanded insulating spaces H3A each having a horizontal length greater than that of each of the plurality of insulating spaces H3 are formed by partially removing portions of the stopper insulating film 322, the blocking dielectric film 324, the charge trap film 330, and the tunneling dielectric film 340 that fill the plurality of indent spaces 310S (see FIG. 16C). As a result, the stopper insulating film 322 may be divided into the plurality of stopper insulating patterns 322P, the blocking dielectric film 324 may be divided into the plurality of blocking dielectric patterns 324P, and the charge trap film 330 may be divided into the plurality of charge trap patterns 330P” and new insulation is provided “Referring to FIG. 16H, the inter-gate insulating pattern 362 filling the plurality of expanded insulating spaces H3A is formed. The inter-gate insulating pattern 362 may be formed of a silicon oxide film, an air-gap, or a combination thereof”, and see that when 362 is formed the insulation can be either silicon oxide film or an air-gap or both.
Thus if Yun is applied to Kimura Fig. 14B a sacrificial is used for “insulators 101A to 101C” and after cutting at least “insulator 102” and “insulator 111”, the opening will look like Yun Fig. 11G i.e. a curvature like that of AG2 and this AG2 can be “silicon oxide film, an air-gap, or a combination thereof”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Kimura to include isolation layers located between the tunnel insulating and the insulating layers, the isolation layers protruding farther toward the tunnel insulating layer than the memory patterns and the blocking patterns, wherein an interface is formed between each of the isolation layers and the tunnel insulating layer, the interface being convexly curved toward the tunnel insulating layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to cut the “insulator 111” into sections so that each bit is electrically isolated from the adjacent bits.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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