DETAILED ACTION
This action is responsive to the following communications: the Application filed August 27, 2024.
Claims 1-20 are pending. Claims 1, 11 and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sim et al. (US 9,042,175).
Regarding independent claim 17, Sim et al. disclose a memory, comprising a memory array (110, figure 1) and a peripheral circuit coupled to the memory array (figure 1), wherein: the peripheral circuit comprises a control logic circuit (150, figure 1) and a page buffer (130, figure 1); the page buffer is coupled with the memory array through a bit line (BL, figure 1); the page buffer comprises a sensing node (SO, figure 5), a first latch (S, figure 5), a second latch (M, figure 1), and a stagger transistor (RST_S); the first latch and the second latch are coupled with a same pull-down transistor (TR1, figure 5) through the stagger transistor; and a control end of (figures 1 and 5) the pull-down transistor (TR1, figure 5) is coupled with the sensing node (SO, figure 5), the sensing node is coupled with the bit line (BLi, figure 5), and a control end of the stagger transistor (RST_S, figure 5) is coupled with the control logic circuit (150, figure 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3 and 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 2017/0323685) in view of YOON (US 2020/0357460).
Regarding independent claim, LEE discloses a memory, comprising a memory array (110, figure 1) and a peripheral circuit (115, figure 1) coupled to the memory array, wherein: the peripheral circuit comprises a control logic circuit (140, figure 1) and a page buffer (PB1, figure 1); the page buffer is coupled with the memory array through a bit line (BL1, figure 1); the control logic circuit is coupled with the page buffer through a signal line (signal line is between control logic and page buffer); the page buffer comprises a first page buffer (PB1, figure 1) and a second page buffer (PB2, figure 1);
However, LEE is silent with respect to the control logic circuit is coupled with the first page buffer through a first stagger control line and is coupled with the second page buffer through a second stagger control line ;and the control logic circuit is configured to: apply an operation voltage to the page buffer through the signal line; and during the application of the operation voltage to the page buffer, apply a control voltage to the first page buffer through the first stagger control line in a first stage and apply the control voltage to the second page buffer through the second stagger control line in a second stage, so as to control the first page buffer and the second page buffer to work in a stagger manner.
YOON discloses the control logic circuit (150, figure 1) is coupled with the first page buffer (131. Figure 3). Note 130 in figure 1 has a plurality of pages buffer that include PAGE BUFFER 131, PAGE BUFFER 132 in figure 3, also para.[0034] disclose: The page buffer circuitry 130 in figure 1 may operate under control of the control logic circuitry 150 in figure 1) through a first stagger control line (SIGL2, figure 3 below) and is coupled with the second page buffer (132, figure 3 below) through a second stagger control line (SIGL1, figure 3) ;and the control logic circuit is configured (150, figure 1, also see para.[0034] discloses: he page buffer circuitry 130 may operate under control of the control logic circuitry 150) to: apply an operation voltage (see paragraphs below) to the page buffer through the signal line (signal line is between page buffer 130 and control logic 150 in figure 1); and during the application of the operation voltage to the page buffer (see paragraphs below), apply a control voltage to the first page buffer through the first stagger control line in a first stage and apply the control voltage to the second page buffer through the second stagger control line in a second stage, so as to control the first page buffer and the second page buffer to work in a stagger manner (see paragraphs below and figures1 and 3).
[0007] According to some example embodiments, a nonvolatile memory device includes a memory cell region including first metal pads and a memory cell array that includes memory cells arranged in rows and columns, and a peripheral circuit region including row decoder circuitry that is connected to the rows of the memory cells through word lines and configured to control voltages of the word lines, and a page buffer circuitry that is connected to the columns of the memory cells through bit lines, and including first transistors configured to transfer voltages of the bit lines to be sensed and second transistors configured to transfer the voltages of the bit lines to be inverted and sensed, wherein the page buffer circuitry is configured to obtain first values by performing a first sensing operation on first bit lines of the bit lines, and obtain second values by performing a second sensing operation on the second bit lines of the bit lines, wherein the peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads.
0035] In an example write operation, the page buffer circuitry 130 may store data to be written into memory cells. The page buffer circuitry 130 may apply voltages to one or more of the plurality of bit lines BL based on the stored data. In an example read operation or in an example verification read operation that may be performed in a write operation or an erase operation, the page buffer circuitry 130 may sense voltages of the bit lines BL and, in some examples, may store a result of the sensing.
Since LEE and YOON et al. are both from the same field of endeavor, the purpose disclosed by YOON would have been recognized in the pertinent art of LEE.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of LEE to teaching of YOON for purpose of using a page buffer to pass a input/output form memory device.
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Regarding claim 2, LEE and YOON disclose the limitation of claim 1.
LEE further discloses wherein the first stage is continuous with the second stage (after the first stage the control continuous to process the second stage).
Regarding claim 3, LEE and YOON disclose the limitation of claim 1.
LEE further discloses wherein a duration of the first stage is equal to a duration of the second stage (when the program voltage was applied first page buffer is same voltage program voltage of second page buffer, therefore a duration of the first stage must be equal a to duration of the second stage).
[0103] One page of the plurality of pages PAGE_0 to PAGE_n is selected according to the program sequence, and a program voltage applying operation for the selected page is performed (at S110). For example, during a program voltage applying operation of the program operation, the page PAGE_0 of the plurality of pages may be selected as the first page. In this case, a program voltage Vpgm may be applied to the page PAGE_0.
Regarding independent claim 11. An operation method of a memory, wherein the memory comprises a memory array and a peripheral circuit coupled to the memory array, the peripheral circuit comprises a page buffer coupled with the memory array through a bit line, the operation method comprising: applying an operation voltage to the page buffer, wherein the page buffer comprises a first page buffer and a second page buffer; and during the application of the operation voltage to the page buffer, applying a control voltage to the first page buffer in a first stage, and applying the control voltage to the second page buffer in a second stage, so as to control the first page buffer and the second page buffer to work in a stagger manner (see rejection of claim 1).
Regarding claim 12. The operation method of claim 11, wherein the first stage is continuous with the second stage (see rejection of claim 2).
Regarding claim 13. The operation method of claim 11, wherein a duration of the first stage is equal to a duration of the second stage (see rejection of claim 3).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 2017/0323685) in view of Sim et al. (US 9,042,175).
Regarding claim 4, LEE discloses the limitation of claim 1.
However, LEE is silent with respect to wherein: the page buffer comprises a sensing node, a first latch, a second latch, and a stagger transistor; the first latch and the second latch are coupled with a same pull-down transistor through the stagger transistor; and a control end of the pull-down transistor is coupled with the sensing node and the sensing node is coupled with the bit line.
Sim et al. disclose wherein: the page buffer comprises a sensing node (SO, figure 5 below), a first latch (S, figure 5 below), a second latch (M, figure 5 below), and a stagger transistor (RST_S, figure 5 below); the first latch and the second latch are coupled with a same pull-down transistor (TR1, figure 5 below) through the stagger transistor (RST_S, figure 5); and a control end of the pull-down transistor is coupled with the sensing node (SO, figure 5 below) and the sensing node is coupled with the bit line (BLi, figure 5 below).
Since LEE and Sim et al. are both from the same field of endeavor, the purpose disclosed by Sim et al. would have been recognized in the pertinent art of KIM.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of LEE to teaching of Sim et al. for purpose of using a plurality of page buffers coupled to a plurality of bit line of the memory cell array and configured to control and sense currents flowing through of bit lines in response to a page buffer sensing signal.
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Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 2017/0323685) in view of Morris et al. (US 2020/0251638).
Regarding claim 9, LEE discloses the limitation of claim1.
However, LEE is silent with respect to wherein a width of the signal line is not less than 0.85 microns.
Morris et al. disclose wherein a width of the signal line is not less than 0.85 microns (see para. [0008] below).
a common signal line in the thin-film circuit layer electrically coupled with a plurality of transistors in thin-film circuit layer, and the plurality of transistors are configured to alternate activation so that current from the common signal line is periodically passed through each of the plurality of transistors; the thin-film circuit layer comprises memory circuits and modulator circuits; a unique address is assigned to each LED in the array of LEDs, and a control signal comprises the unique address and an operation signal to control operation of a selected LED in the array of LEDs; the operation signal is configured to control a magnitude of current that flows through the selected LED, and the operation signal comprises a digital signal representing a percentage of a time within a time period for which current flows to the selected LED; and/or spacing between centers of LEDs are spaced no further apart than three microns.
Since LEE and Morris et al. are both from the same field of endeavor, the purpose disclosed by Morris et al. would have been recognized in the pertinent art of KIM.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of LEE to teaching of Morris et al. for purpose of using LED to be more closely spaced, to enable a higher resolution display.
Regarding claim 10, LEE disclose the limitation of claim 1.
However, LEE silent with respect to wherein the signal line is disposed at a metal layer5 (M5( layer or a top metal (TM) layer.
Morris et al. disclose wherein the signal line is disposed at a metal layer5 (M5( layer or a top metal (TM) layer (see para.[0008] below)
[0008] According to some embodiments, an apparatus comprises an array of light emitting diodes (LEDs); a thin-film circuit layer deposited on the array of LEDs; and a backplane coupled with the thin-film circuit layer using a plurality of metal bonds. The array of LEDs is made of a layered epitaxial structure including a first doped semiconductor layer, a second doped semiconductor layer, and a light-emitting layer between the first doped semiconductor layer and the second doped semiconductor layer. The array of LEDs is a support structure for the thin-film circuit layer. The thin-film circuit layer comprises circuitry for controlling operation of LEDs in the array of LEDs. The backplane has drive circuitry for supplying electrical current to the thin-film circuit layer through the plurality of metal bonds. A number of the plurality of metal bonds is less than a number of LEDs in the array of LEDs. In some embodiments, the array of LEDs has a light-emitting side and a side opposite the light-emitting side, and the thin-film circuit layer is deposited on the side opposite the light-emitting side of the array of LEDs, and the thin-film circuit layer comprises transistors and capacitors interconnected to form pixel circuits for controlling operation of LEDs in the array of LEDs; the pixel circuits implement analog, pulse-code modulation, or pulse-width modulation for controlling intensity of LEDs in the array of LEDs; a storage capacitor of a pixel circuit is configured to be coupled to a dateline by one or more selection signals; pixel circuits are interconnected to reduce a number of metal bonds between the backplane and the think-film circuit layer; a single pixel circuit is connected to multiple row selection signals; the backplane is configured to transmit a global signal through a metal bond, of the plurality of metal bonds, to the thin-film circuit layer, wherein the global signal comprises one or more of a row dataline, a column dataline, an analog bias, a voltage supply, a pulse clocks, or test enablement features; no transistor in the thin-film circuit layer is used to charge/discharge a global net; the thin-film circuit layer comprises a selector multiplexor; the selector multiplexor comprises a common signal line in the thin-film circuit layer electrically coupled with a plurality of transistors in thin-film circuit layer, and the plurality of transistors are configured to alternate activation so that current from the common signal line is periodically passed through each of the plurality of transistors; the thin-film circuit layer comprises memory circuits and modulator circuits; a unique address is assigned to each LED in the array of LEDs, and a control signal comprises the unique address and an operation signal to control operation of a selected LED in the array of LEDs; the operation signal is configured to control a magnitude of current that flows through the selected LED, and the operation signal comprises a digital signal representing a percentage of a time within a time period for which current flows to the selected LED; and/or spacing between centers of LEDs are spaced no further apart than three microns.
Since LEE and Morris et al. are both from the same field of endeavor, the purpose disclosed by Morris et al. would have been recognized in the pertinent art of KIM.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of LEE to teaching of Morris et al. for purpose of using LED to be more closely spaced, to enable a higher resolution display.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sim et al. (US 9,042,175) in view of LEE (US 2017/0323685)).
Regarding claim 18, Sim et al. disclose the limitation of claim 17.
However, Sim et al. are silent with respect to wherein: the first latch and the second latch are latch circuits; the latch circuit comprises a first inverter, a second inverter, a setting transistor, and a resetting transistor.
LEE discloses wherein: the first latch (LATT, figure 3 below) and the second latch (LTM, figure 3 below) are latch circuits; the latch circuit comprises a first inverter (figure 3), a second inverter (figure 3), a setting transistor (N8, figure 3), and a resetting transistor (N7, figure 3).
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Since Sim et al. and LEE are both from the same field of endeavor, the purpose disclosed by LEE would have been recognized in the pertinent art of Sim et al.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Sim et al. to teaching of LEE for purpose of using a plurality of page buffers coupled to a plurality of bit line of the memory cell array and configured to control and sense currents flowing through of bit lines in response to a page buffer sensing signal.
Allowable Subject Matter
Claims 5-8, 14-16 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art made of record and considered pertinent to the applicant’s disclosure does not reach the claimed limitation of a control end of the stagger transistor in the second page buffer is coupled with the second stagger control line, and the control logic circuit is configured to: during application of the operation voltage to the first latch or the second latch in the page buffer through the signal line, apply the control voltage to the control end of the stagger transistor in the first page buffer through the first stagger control line, so as to control the stagger transistor in the first page buffer to be turned on; or apply the control voltage to the control end of the stagger transistor in the second page buffer through the second stagger control line, so as to control the stagger transistor in the second page buffer to be turned on in combination with other limitations thereof as is recited in the claim.
Regarding claim 6, the prior art made of record and considered pertinent to the applicant’s disclosure does not reach the claimed limitation of a setting transistor, and a resetting transistor, wherein: an input end of the first inverter is coupled with an output end of the second inverter and an input end of the second inverter is coupled with an output end of the first inverter; a first end of the setting transistor is coupled with the input end of the first inverter; a first end of the resetting transistor is coupled with the input end of the second inverter; a second end of the setting transistor and a second end of the resetting transistor are coupled with a first end of the stagger transistor; a second end of the stagger transistor is coupled with a first end of the pull-down transistor; and a second end of the pull-down transistor is grounded a setting transistor, and a resetting transistor, wherein: an input end of the first inverter is coupled with an output end of the second inverter and an input end of the second inverter is coupled with an output end of the first inverter; a first end of the setting transistor is coupled with the input end of the first inverter; a first end of the resetting transistor is coupled with the input end of the second inverter; a second end of the setting transistor and a second end of the resetting transistor are coupled with a first end of the stagger transistor; a second end of the stagger transistor is coupled with a first end of the pull-down transistor; and a second end of the pull-down transistor is grounded in combination with other limitations thereof as is recited in the claim. Claims 7-8 depend on claim 6.
Regarding claim 14, the prior art made of record and considered pertinent to the applicant’s disclosure does not reach the claimed limitation of applying the operation voltage to the first latch or the second latch in the page buffer, wherein the first latch and the second latch are coupled with a same pull-down transistor through the stagger transistor, and a control end of the pull-down transistor is coupled with the sensing node; and during application of the operation voltage to the first latch or the second latch, applying the control voltage to a control end of the stagger transistor in the first page buffer, so as to control the stagger transistor in the first page buffer to be turned on; or applying the control voltage to a control end of the stagger transistor in the second page buffer, so as to control the stagger transistor in the second page buffer to be turned on in combination with other limitations thereof as is recited in the claim. Claims 15-16 depend on claim 14.
Regarding claim 19, the prior art made of record and considered pertinent to the applicant’s disclosure does not reach the claimed limitation of an input end of the first inverter is coupled with an output end of the second inverter and an input end of the second inverter is coupled with an output end of the first inverter; a first end of the setting transistor is coupled with the input end of the first inverter; a first end of the resetting transistor is coupled with the input end of the second inverter; a second end of the setting transistor and a second end of the resetting transistor are coupled with a first end of the stagger transistor; a second end of the stagger transistor is coupled with a first end of the pull-down transistor; and a second end of the pull-down transistor is grounded in combination with other limitations thereof as is recited in the claim. Claim 20 depends on claim 19.
Conclusion
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/MINH D DINH/Examiner, Art Unit 2827 /AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827