DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0,240,195 (Shiu et al; hereinafter Shiu) in view of Veeck (US 5,339,218).
Regarding claim 1, Shiu discloses a surface-mount technology (SMT) device (electronic device 10; figs. 1, 2 (¶ [0022]) including SMT components (¶ [0030]) comprising: “an electrical element (impedance matching circuitry and/or radio frequency transceiver circuitry (paras. [0029]-[0030]);
a plurality of terminals connected to the electrical element connected to the electrical element (a plurality of terminals, e.g. positive antenna feed terminal and ground antenna feed terminal (para. [0038]), the antenna terminals are connected to the radio frequency transceiver circuitry and/or impedance matching circuitry via transmission lines 42; Fig. 2; paras. [0030], [0038]); and
a body configured to support the electrical element and the plurality of terminals (body of electronic device 10 supports the radio frequency transceiver circuitry and/or impedance matching circuitry and the antenna terminals; Fig. 1; Paragraphs [0023], [0030] and [0038]), the body having a rectangular cuboid shape with a length, a width, and a height that is greater than the width (body of electronic device 10 has a rectangular cuboid shape, with a length (side along line 20 in Fig. 1), a width (side along line 22 in Fig. 1) and a height (18+16 along line 26 in Fig. 1) that is greater than the width (side along line 22 in Fig. 1) (see Fig. 1; paras. [0033], [0034]),
the body including a base plane (electronic device 10 have circuits implemented via SMT (¶ [0030]; Figs. 1, 2), wherein components can be mounted on a region 14 (base panel) (¶ [0025]) of the SMT device (electronic device 10 including SMT (Figs. 1, 2; paras. [0022], [0030])”. Shiu do not explicitly disclose a base plane configured to allow surface mounting of the device. In the same field of endeavor, Veeck discloses a base plane configured to allow surface mounting of the device (a surface mountable microelectronic device comprising a metallic base member to allow surface mounting of the device; col 1, lines 23-30; abstract). It would have been obvious to a person of ordinary skill in the art at the time the invention was filed to modify the system of Chiu with the system of Veeck in order to enable surface mount of microelectronic device onto a base plane in a secure manner that extends life of a circuit board assembly using thermally conductive insulating layer to protect and insulate the device from external environmental factors.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claims 1 and 2 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 17 of U.S. Patent No. 10,084,503. Although the claims at issue are not identical, they are not patentably distinct from each other because they claim similar subject matter as shown below:
Current Application #: 18/817,194
U.S. Patent No. 10,084,503
1. A surface-mountable device comprising: an electrical element; a plurality of terminals connected to the electrical element; and
a body configured to support the electrical element and the plurality of terminals, the body having a rectangular cuboid shape with a length, a width, and a height that is greater than the width, the body including a base plane configured to allow surface mounting of the device.
1. A surface-mount technology (SMT) device comprising: an electrical element implemented in a plurality of layers, and including a capacitance element or an inductance element; a body including a plurality of substrate layers configured to support respective layers of the electrical element, the body having a rectangular cuboid shape with a length, a width, and a height that is greater than the width, the body including a base plane configured to allow surface mounting of the SMT device onto a packaging substrate or a circuit board; and first and second terminals implemented on the base plane and connected to the electrical element, and configured to provide electrical connections between the electrical element and the packaging substrate or the circuit board when the SMT device is mounted thereon
2. A method for fabricating a surface-mountable device, the method comprising: forming or providing an electrical element; forming a body to support the electrical element, the body having a rectangular cuboid shape with a length, a width, and a height that is greater than the width, the body including a base plane configured to allow surface mounting of the device; and forming first and second terminals on the base plane, such that the first and second terminals are electrically connected to the electrical element.
17. A packaged electronic module comprising: a packaging substrate configured to receive a plurality of components; a semiconductor die mounted on the packaging substrate, the semiconductor die including an integrated circuit; and a surface-mount technology (SMT) device mounted on the packaging substrate, and including an electrical element implemented in a plurality of layers, and including a capacitance element or an inductance element; a body having a plurality of substrate layers configured to support respective layers of the electrical element, the body having a rectangular cuboid shape with a length, a width, and a height that is greater than the width, the body including a base plane; and first and second terminals implemented on the base plane and connected to the electrical element, and configured to provide electrical connections between the electrical element and the packaging substrate.
6. Claim 1 and 2 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 2 of U.S. Patent No. 12,074,628. Although the claims at issue are not identical, they are not patentably distinct from each other because they claim similar subject matter as shown below:
Current Application #: 18/817,194
Patent # 12,074,628
1. A surface-mountable device comprising: an electrical element; a plurality of terminals connected to the electrical element; and
a body configured to support the electrical element and the plurality of terminals, the body having a rectangular cuboid shape with a length, a width, and a height that is greater than the width, the body including a base plane configured to allow surface mounting of the device.
1. A surface-mount device comprising: an electrical element including a capacitance element or an inductance element; a body configured to support the electrical element and having a rectangular cuboid shape with a length, a width, and a height that is greater than the width, the body including a base plane configured to allow mounting of the surface-mount device; and first and second terminals implemented on the base plane and connected to the electrical element to be capable of providing electrical connections between the electrical element and a packaging substrate or a circuit board when the surface-mount device is mounted thereon.
2. A method for fabricating a surface-mountable device, the method comprising: forming or providing an electrical element; forming a body to support the electrical element, the body having a rectangular cuboid shape with a length, a width, and a height that is greater than the width, the body including a base plane configured to allow surface mounting of the device; and forming first and second terminals on the base plane, such that the first and second terminals are electrically connected to the electrical element.
2. A packaged module comprising: a packaging substrate; and a surface-mount device that includes an electrical element having a capacitance element or an inductance element, and a body configured to support the electrical element and having a rectangular cuboid shape with a length, a width, and a height that is greater than the width, the body including a base plane configured to allow mounting of the surface-mount device, the surface-mount device further including first and second terminals implemented on the base plane and connected to the electrical element to provide electrical connections between the electrical element and the packaging substrate.
Claim 1 and 2 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 and 1 of U.S. Patent No. 11,616,526. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of US Patent No. 11,616,526 claim similar subject matter as shown below:
Current Application #: 18/817,194
US Patent No. 11,616,526
1. A surface-mountable device comprising: an electrical element; a plurality of terminals connected to the electrical element; and
a body configured to support the electrical element and the plurality of terminals, the body having a rectangular cuboid shape with a length, a width, and a height that is greater than the width, the body including a base plane configured to allow surface mounting of the device.
17. A method for fabricating a packaged electronic module, the method comprising: forming or providing a packaging substrate configured to receive a plurality of components; mounting a semiconductor die on the packaging substrate, the semiconductor die including an integrated circuit; and mounting a surface-mount technology (SMT) device on the packaging substrate, the SMT device including an electrical element implemented in a plurality of layers, and including a capacitance element or an inductance element; a body having a plurality of substrate layers configured to support respective layers of the electrical element, the body having a rectangular cuboid shape with a length, a width, and a height that is greater than the width, the body including a base plane; and first and second terminals implemented on the base plane and connected to the electrical element, and configured to provide electrical connections between the electrical element and the packaging substrate.
2. A method for fabricating a surface-mountable device, the method comprising: forming or providing an electrical element; forming a body to support the electrical element, the body having a rectangular cuboid shape with a length, a width, and a height that is greater than the width, the body including a base plane configured to allow surface mounting of the device; and forming first and second terminals on the base plane, such that the first and second terminals are electrically connected to the electrical element.
1. A method for fabricating a surface-mount technology (SMT) device, the method comprising: implementing an electrical element in a plurality of layers to include a capacitance element or an inductance element; forming a body with a plurality of substrate layers to support respective layers of the electrical element, the body having a rectangular cuboid shape with a length, a width, and a height that is greater than the width, the body including a base plane configured to allow surface mounting of the SMT device onto a packaging substrate or a circuit board; and forming first and second terminals on the base plane, such that the first and second terminals are electrically connected to the electrical element.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LANA N LE whose telephone number is (571) 272-7891. The examiner can normally be reached M-F 8:30am - 4:30pm.
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/LANA N LE/Primary Examiner, Art Unit 2648
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