DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Amendment on 08/02/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 10 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Cheng et al. (US 10,345,847), hereinafter Cheng.
Regarding claim 1, Cheng discloses (see figures 1-12) a low-dropout (LDO) regulator (figure 2, part 200 [as LDO 20 at figure 1]), comprising: a reference voltage generation circuit (figure 2, part reference voltage generation circuit that generates Vbg’), arranged to generate at least one reference voltage (figures 2 and 4, part Vbg’); an operational amplifier (figure 2, part inside of 200 [figure 1, part operational amplifier at 20]), coupled to the reference voltage generation circuit (figure 2, part reference voltage generation circuit that generates Vbg’), arranged to control an output voltage of the LDO regulator (figure 2, part inside of 200 [figure 1, part output voltage at Vrefp]) via negative feedback in a LDO regulating mode (figure 2, part inside of 200 [figure 1, part negative feedback at between operational amplifier and transistor]) of the LDO regulator (figure 2, part 200 [as LDO 20 at figure 1]); a transistor (figure 2, part inside of 200 [figure 1, part transistor at 20]), coupled to the operational amplifier (figure 2, part inside of 200 [figure 1, part operational amplifier at 20]), arranged to generate the output voltage of the LDO regulator (figure 2, part inside of 200 [figure 1, part output voltage at Vrefp]) under control of the operational amplifier in the LDO regulating mode (figure 2, part inside of 200 [figure 1, part operational amplifier at 20]), for further use (figure 2, part 200 [as LDO 20 at figure 1]); and a multiphase configuration switching control circuit (figure 2, part multiphase configuration switching control circuit generated by 120 and 150), coupled to the reference voltage generation circuit (figure 2, part reference voltage generation circuit that generates Vbg’), the operational amplifier (figure 2, part inside of 200 [figure 1, part operational amplifier at 20]) and the transistor (figure 2, part inside of 200 [figure 1, part transistor at 20]) (column 3; lines 33-57; The switch circuit 140 is arranged to generate a bandgap current Ibg according to the reference current Iref, and to generate a bandgap voltage Vbg′ by outputting the bandgap current Ibg to a resistor R1, wherein the bandgap voltage Vbg′ is coupled to an LDO 200), arranged to perform multiphase configuration switching control (figure 2, part multiphase configuration switching control circuit generated by 120 and 150; through TRI and SCTRL) to perform multiple configuring operations on circuit architecture of the LDO regulator (figure 2, part 200 [as LDO 20 at figure 1]); wherein: the multiphase configuration switching control circuit (figure 2, part multiphase configuration switching control circuit generated by 120 and 150) performs a first configuring operation on the circuit architecture of the LDO regulator (figure 2, part 200 [as LDO 20 at figure 1]) to enable a first dedicated current path (figures 2 and 4, part first dedicated current path at Ibg in first phase from t2 passing 0.855 to peak) corresponding to a first phase path (figure 4, part first phase from t2 passing 0.855 to peak), to allow a target reference voltage (figures 2 and 4, part Vbg’) used in the LDO regulating mode (figure 2, part 200 [as LDO 20 at figure 1]) to reach a first predetermined range after the first configuring operation is performed (figures 2 and 4, part first predetermined range of Vbg’ from t2 passing 0.855 to peak); the multiphase configuration switching control circuit (figure 2, part multiphase configuration switching control circuit generated by 120 and 150) performs a second configuring operation on the circuit architecture of the LDO regulator (figure 2, part 200 [as LDO 20 at figure 1]) to enable a second dedicated current path (figures 2 and 4, part second dedicated current path at Ibg in second phase from peak to 0.855) corresponding to a second phase (figure 4, part second phase from peak to 0.855), to allow the target reference voltage (figures 2 and 4, part Vbg’) to reach a second predetermined range after the second configuring operation is performed (figures 2 and 4, part second predetermined range of Vbg’ from peak to 0.855); and the multiphase configuration switching control circuit (figure 2, part multiphase configuration switching control circuit generated by 120 and 150) performs a third configuring operation on the circuit architecture of the LDO regulator (figure 2, part 200 [as LDO 20 at figure 1]), to allow the target reference voltage (figures 2 and 4, part Vbg’) to be used as a reference voltage input into the operational amplifier(figures 2 and 4, part Vbg’ [0.9 V] input to upper terminal of operational amplifier at LDO 200 [Figure 1, part operational amplifier]) in the LDO regulating mode after the third configuring operation is performed (figures 2 and 4, part third configuring operation that generates Vbg’ go to steady voltage value of 0.9) (columns 3-5; lines 35-67, 1-67 and 1-56).
Regarding claim 2, Cheng discloses everything claimed as applied above (see claim 1). Further, Cheng discloses (see figures 1-12) reaching the first predetermined range (figures 2 and 4, part first predetermined range of Vbg’ from t2 passing 0.855 to peak) comprises exceeding a second voltage level (figures 2 and 4, part exceeding 0.855), and reaching the second predetermined range (figures 2 and 4, part second predetermined range of Vbg’ from peak to 0.855) comprises approaching a first voltage level (figures 2 and 4, part approaching 0.9), wherein the second voltage level (figures 2 and 4, part 0.855) is less than the first voltage level (figures 2 and 4, part 0.9) (column 5; lines 1-56).
Regarding claim 3, Cheng discloses everything claimed as applied above (see claim 2). Further, Cheng discloses (see figures 1-12) at least one reference voltage (figures 2 and 4, part Vbg’) comprises a first reference voltage (figures 2 and 4, part first reference voltage at 0.9) equal to the first voltage level (figures 2 and 4, part 0.9) and a second reference voltage (figures 2 and 4, part first reference voltage at 0.855) equal to the second voltage level (figures 2 and 4, part 0.855).
Regarding claim 4, Cheng discloses everything claimed as applied above (see claim 1). Further, Cheng discloses (see figures 1-12) performing the first configuring operation (figures 2 and 4, part first predetermined range of Vbg’ from t2 passing 0.855 to peak) comprises: enabling the first dedicated current path (figures 2 and 4, part first dedicated current path at Ibg in first phase from t2 passing 0.855 to peak) corresponding to the first phase path (figure 4, part first phase from t2 passing 0.855 to peak) to perform a first preliminary setting operation on the target reference voltage (figures 2 and 4, part Vbg’ from t2 passing 0.855 to peak) according to a power supply voltage (figure 2, part VDD), for accelerating the target reference voltage (figures 2 and 4, part Vbg’) reaching the first predetermined range (figures 2 and 4, part first predetermined range of Vbg’ from t2 passing 0.855 to peak).
Regarding claim 10, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 10,345,847), hereinafter Cheng, in view of Lee et al. (US 2023/0221747), hereinafter Lee.
Regarding claim 6, Cheng discloses everything claimed as applied above (see claim 1). Further, Cheng discloses (see figures 1-12) reaching the first predetermined range (figures 2 and 4, part first predetermined range of Vbg’ from t2 passing 0.855 to peak) comprises exceeding a second voltage level (figures 2 and 4, part exceeding 0.855); and the at least one reference voltage (figures 2 and 4, part Vbg’) comprises a second reference voltage (figures 2 and 4, part second reference voltage Vbg’ of 0.855) equal to the second voltage level (figures 2 and 4, part 0.855); and performing the first configuring operation (figure 4, part first configuring operation at first phase from t2 passing 0.855 to peak) comprises: coupling a first input terminal and a second input terminal of the operational amplifier (figure 2, part inside of 200 [figure 1, part operational amplifier at 20; upper and lower input terminals]) to the target reference voltage (figures 2 and 4, part Vbg’), respectively, to make the operational amplifier act as a comparator (figure 2, part inside of 200 [figure 1, part operational amplifier at 20]) (column 5; lines 1-56). However, Cheng does not expressly disclose coupling a first input terminal and a second input terminal of the operational amplifier to the target reference voltage and the second reference voltage, respectively, to make the operational amplifier act as a comparator, for comparing the target reference voltage and the second reference voltage.
Lee teaches (see figures 1-12) coupling a first input terminal and a second input terminal of the operational amplifier (figure 4A, part 411; upper and lower input terminals) to the target reference voltage (figure 4B, part target reference voltage at upper input terminal of 411) and the second reference voltage (figure 4B, part second reference voltage generated by Vin at lower input terminal of 411), respectively, to make the operational amplifier act as a comparator (figure 4B, part 411), for comparing the target reference voltage (figure 4B, part target reference voltage at upper input terminal of 411) and the second reference voltage (figure 4B, part second reference voltage generated by Vin at lower input terminal of 411) (paragraphs [0047]-[0053]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the LDO regulator of Cheng with the controller features as taught by Lee and obtain reaching the first predetermined range comprises exceeding a second voltage level, and the at least one reference voltage comprises a second reference voltage equal to the second voltage level; and performing the first configuring operation comprises: coupling a first input terminal and a second input terminal of the operational amplifier to the target reference voltage and the second reference voltage, respectively, to make the operational amplifier act as a comparator, for comparing the target reference voltage and the second reference voltage, because it provides more efficient control to prevent distortion (paragraph [0004]).
Regarding claim 7, Cheng and Lee teach everything claimed as applied above (see claim 6). Further, Cheng discloses (see figures 1-12) performing the first configuring operation (figure 4, part first configuring operation at first phase from t2 passing 0.855 to peak) further comprises: the first terminal of the transistor (figure 2, part inside of 200 [figure 1, part lower terminal of transistor at 20]) is arranged to output the output voltage of the LDO regulator (figure 2, part inside of 200 [figure 1, part output voltage at Vrefp]). However, Cheng does not expressly disclose disconnecting a negative feedback path between the second input terminal of the operational amplifier and a first terminal of the transistor to disable the negative feedback path used in the LDO regulating mode, wherein in the LDO regulating mode, the first terminal of the transistor is arranged to output the output voltage of the LDO regulator.
Lee teaches (see figures 1-12) performing the first configuring operation (figure 4B) further comprises: disconnecting (figure 4B, part through open Tr1) a negative feedback path between the second input terminal of the operational amplifier (figure 4B, part lower input terminal of 411) and a first terminal of the transistor (figure 4B, part lower terminal of transistor supply Vout) to disable the negative feedback path used in the LDO regulating mode (figure 4B, part through open Tr1), wherein in the LDO regulating mode (figure 4B, part 410), the first terminal of the transistor (figure 4B, part transistor supply Vout) is arranged to output the output voltage of the LDO regulator (figure 4B, part Vout) (paragraphs [0047]-[0053]; the LDO regulator 410 may operate in the first operation mode).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the LDO regulator of Cheng with the controller features as taught by Lee and obtain performing the first configuring operation further comprises: disconnecting a negative feedback path between the second input terminal of the operational amplifier and a first terminal of the transistor to disable the negative feedback path used in the LDO regulating mode, wherein in the LDO regulating mode, the first terminal of the transistor is arranged to output the output voltage of the LDO regulator, because it provides more efficient control to prevent distortion (paragraph [0004]).
Allowable Subject Matter
Claims 5, 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art (which has been made of record) fail to disclose (by themselves or in combination):
Regarding claim 5, reaching the first predetermined range comprises exceeding a second voltage level, and the at least one reference voltage comprises a second reference voltage equal to the second voltage level; and performing the first configuring operation further comprises: coupling multiple input terminals of the operational amplifier to the target reference voltage and the second reference voltage, respectively, to make the operational amplifier act as a comparator, for comparing the target reference voltage and the second reference voltage; wherein the LDO regulator further comprises: an automatic fast-set control circuit, coupled to an output terminal of the operational amplifier, arranged to receive a comparison result of the target reference voltage and the second reference voltage from the operational amplifier, to generate a control signal according to the comparison result; and a current control circuit, coupled to the automatic fast-set control circuit, arranged to control a current on the first dedicated current path according to the control signal, for accelerating the target reference voltage reaching the first predetermined range;
Regarding claim 8, performing the second configuring operation further comprises: stopping coupling the second input terminal of the operational amplifier to the second reference voltage, and coupling the second input terminal of the operational amplifier to a first terminal of the transistor, to enable a negative feedback path used in the LDO regulating mode, wherein in the LDO regulating mode, the first terminal of the transistor is arranged to output the output voltage of the LDO regulator; disabling the first dedicated current path corresponding to the first phase, wherein the first dedicated current path is coupled between a power line and the first input terminal of the operational amplifier in the first phase, and is no longer coupled between the power line and the first input terminal of the operational amplifier in the second phase; and enabling the second dedicated current path corresponding to the second phase to make the first input terminal of the operational amplifier be coupled to the second reference voltage, to forcibly set the target reference voltage to be equal to the second reference voltage, for reducing any deviation of the target reference voltage generated in the first phase with respect to the second predetermined range to accelerate the target reference voltage reaching the second predetermined range;
Regarding claim 9, this claim 9 is dependent claim of claim 8, therefore, it is objected by the same reason presented above;
in combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Response to Arguments
Applicant's arguments filed 08/02/2026 have been fully considered but they are not persuasive.
Applicant’s argues on pages 7-8 of the Applicant's Response (“Cheng Does Not Disclose Two Structurally Distinct Dedicated Current Paths… Accordingly, Cheng fails to disclose or suggest the claimed plurality of dedicated current paths, and therefore does not anticipate claim 1”).
The Examiner respectfully disagrees with Applicant’s arguments, because Cheng discloses (based on claimed limitation) the multiphase configuration switching control circuit (figure 2, part multiphase configuration switching control circuit generated by 120 and 150) performs a first configuring operation on the circuit architecture of the LDO regulator (figure 2, part 200 [as LDO 20 at figure 1]) to enable a first dedicated current path (figures 2 and 4, part first dedicated current path at Ibg in first phase from t2 passing 0.855 to peak) corresponding to a first phase path (figure 4, part first phase from t2 passing 0.855 to peak), to allow a target reference voltage (figures 2 and 4, part Vbg’) used in the LDO regulating mode (figure 2, part 200 [as LDO 20 at figure 1]) to reach a first predetermined range after the first configuring operation is performed (figures 2 and 4, part first predetermined range of Vbg’ from t2 passing 0.855 to peak); the multiphase configuration switching control circuit (figure 2, part multiphase configuration switching control circuit generated by 120 and 150) performs a second configuring operation on the circuit architecture of the LDO regulator (figure 2, part 200 [as LDO 20 at figure 1]) to enable a second dedicated current path (figures 2 and 4, part second dedicated current path at Ibg in second phase from peak to 0.855) corresponding to a second phase (figure 4, part second phase from peak to 0.855), to allow the target reference voltage (figures 2 and 4, part Vbg’) to reach a second predetermined range after the second configuring operation is performed (figures 2 and 4, part second predetermined range of Vbg’ from peak to 0.855). In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., Cheng Does Not Disclose Two Structurally Distinct Dedicated Current Paths… (a) a first dedicated current path, which originates from a power line (e.g., the power line PWR) and passes through a current control circuit (e.g., the current control circuit 130) and a switch circuit (e.g., the switch circuit SW3); and (b) a second dedicated current path, which originates from a reference voltage converter (e.g., the reference voltage converter 103) and passes through another switch circuit (e.g., the switch circuit SW1)) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Therefore, Cheng meets with the claimed limitation. It should be noted that broad claim language as recited does not define the structures used to generates the first dedicated current path and the second dedicated current path. The examiner suggests the applicant to positively recite in the claim language the specific the structures used to generates the first dedicated current path and the second dedicated current path (example: a) a first dedicated current path, which originates from a power line (e.g., the power line PWR) and passes through a current control circuit (e.g., the current control circuit 130) and a switch circuit (e.g., the switch circuit SW3); and (b) a second dedicated current path, which originates from a reference voltage converter (e.g., the reference voltage converter 103) and passes through another switch circuit (e.g., the switch circuit SW1)), in order to distinguish the invention from the prior art of record.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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