Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of species 2 in the reply filed on 01/25/2026 is acknowledged. Applicants’ argument regarding election of species 2 is found persuasive and claims 1-8 are examined. Applicants’ argument regarding species 1 and 3-7 are found persuasive and claims 9-14 are examined.
Applicant's election with traverse of species 8 in the reply filed on 01/25/2026 is acknowledged. The traversal is on the ground(s) that biasing circuit 700 utilize the core semiconductor device of the species 1, 2, 5 and 7. This is not found persuasive because claims 1 – 14 do not disclose the use of a biasing circuit or biasing voltage. Therefore claims 15-20 are withdrawn from consideration.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 8-14 rejected under 35 U.S.C. 103 as being unpatentable over Onishi et al. (US 20160241011 A1 and Onishi hereinafter.)
Regarding claim 1, Onishi discloses a semiconductor device [fig. 3], comprising: a first transistor [30] controlled by a first switch signal [Vgr] and configured to be conducted in a first enable period [t0, fig. 5, Vgr high]; a second transistor [20] controlled by a second switch signal [Vgn] and configured to be conducted at least in a second enable period [fig. 2, Tnon]. A third transistor [10] controlled by a third switch signal [Vgp] and configured to be conducted at least in a third enable period [fig. 2, Tpon], wherein the second transistor is coupled between the first transistor and the third transistor [as shown].
Onishi discloses the claimed invention except for an enable period for a switch comprising a delay. Onishi discloses delaying turning off a switch [para. 58-60, 62 and 67], therefore it would be obvious to one trained in the art to have an enable period for a switch including a delay. Applicant has provided no disclosure pertaining to the mechanics of the delay and/or how the delay is produced. It would be a simple practice to those trained in the art to disclose timing periods of any given switch without further details.
Regarding claim 2, Onishi discloses further wherein the second transistor keeps conducted in the first enable period [as shown in fig. 2], and the third transistor keeps conducted in the second enable period [as shown in fig. 2].
Regarding claim 3, Onishi discloses the claimed invention except for the second transistor has an on-state resistance, and the on-state resistance in the third enable period is lower than the on-state resistance in the first delay period, the on-state resistance in the second delay period, the on-state resistance in the third delay period, and the on-state resistance in the fourth delay period. Onishi discloses lowering or increasing on-resistance of transistors [para. 38, 41 and 68]. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have on-resistances of one or transistors to be higher or lower from other transistors since It was known in the art due to the inherent nature of transistors having an on-resistance when operated. Further, it has been held that discovering an optimum value of a result effective variable involves only routine Skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 4, Onishi discloses the claimed invention except for the second transistor has a threshold voltage and a breakdown voltage, wherein a voltage of the second switch signal is between the threshold voltage and the breakdown voltage in the first delay period, the second delay period, the third delay period, and the fourth delay period, wherein the breakdown voltage is between the voltage of the second switch signal and the threshold voltage in the third enable period. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a transistor featuring a threshold voltage and a breakdown voltage, wherein a voltage of a switch signal is between the threshold voltage and the breakdown voltage since It was known in the art. Further, it has been held that discovering an optimum value of a result effective variable involves only routine Skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 5, Onishi discloses the claimed invention except for the second transistor is conducted in the second enable period and switched off in the first delay period and the second delay period, wherein the third transistor is conducted in the third enable period and switched off in the first delay period, the second delay period, the third delay period, and the fourth delay period. Onishi discloses delaying turning off a switch [para. 58-60, 62 and 67], therefore it would be obvious to one trained in the art to have an enable period for a switch including a delay. Applicant has provided no disclosure pertaining to the mechanics of the delay and/or how the delay is produced. It would be a simple practice to one trained in the art to have differing timing periods of any given switch.
Regarding claim 6, Onishi discloses the claimed invention except for wherein a breakdown voltage of the third transistor is higher than a breakdown voltage of the first transistor and higher than a breakdown voltage of the second transistor. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a transistor featuring a threshold voltage and a breakdown voltage, wherein a voltage of a switch signal is between the threshold voltage and the breakdown voltage since It was known in the art.
Regarding claim 8, Onishi discloses further wherein the first transistor, the second transistor, and the third transistor are all P-type transistors or all N-type transistors [as shown in fig. 6].
Regarding claim 9, Onishi discloses [fig. 3] an amplifier [101], comprising: a first semiconductor device [101]; wherein the first semiconductor device comprises a first transistor [30] controlled by a first switch signal [Vgr] and configured to be conducted in a first enable period [fig. 5, Vgr high during t0 to t2]; a second transistor [20] controlled by a second switch signal [Vgn] and configured to be conducted at least in a second enable period [fig. 2, Tnon]. A third transistor [10] controlled by a third switch signal [Vgp] and configured to be conducted at least in a third enable period [fig. 2, Tnon], wherein the second transistor is coupled between the first transistor and the third transistor [as shown].
Regarding claim 10, Onishi discloses further wherein the second transistor keeps conducted in the first enable period [as shown in fig. 2], and the third transistor keeps conducted in the second enable period [as shown in fig. 2].
Regarding claim 11, Onishi disclose the claimed invention except for the second transistor has an on-state resistance, and the on-state resistance in the third enable period is lower than the on-state resistance in the first delay period, the on-state resistance in the second delay period, the on-state resistance in the third delay period, and the on-state resistance in the fourth delay period. Onishi discloses lowering or increasing on-resistance of transistors [para. 38, 41 and 68]. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have on-resistances of one or transistors to be higher or lower from other transistors since It was known in the art due to the inherent nature of transistors having an on-resistance when operated. Further, it has been held that discovering an optimum value of a result effective variable involves only routine Skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 12, Onishi discloses the claimed invention except for wherein the second transistor has a threshold voltage and a breakdown voltage, wherein a voltage of the second switch signal is between the threshold voltage and the breakdown voltage in the first delay period, the second delay period, the third delay period, and the fourth delay period, wherein the breakdown voltage is between the voltage of the second switch signal and the threshold voltage in the third enable period. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a transistor featuring a threshold voltage and a breakdown voltage, wherein a voltage of a switch signal is between the threshold voltage and the breakdown voltage since It was known in the art.
Regarding claim 13, Onishi discloses the claimed invention except for wherein the second transistor is conducted in the second enable period and switched off in the first delay period and the second delay period, wherein the third transistor is conducted in the third enable period and switched off in the first delay period, the second delay period, the third delay period, and the fourth delay period. Onishi discloses delaying turning off a switch [para. 58-60, 62 and 67], therefore it would be obvious to one trained in the art to have an enable period for a switch including a delay. Applicant has provided no disclosure pertaining to the mechanics of the delay and/or how the delay is produced. It would be a simple practice to one trained in the art to have differing timing periods of any given switch.
Regarding claim 14, Onishi discloses the claimed invention except for wherein a breakdown voltage of the third transistor is higher than a breakdown voltage of the first transistor and higher than a breakdown voltage of the second transistor. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a transistor featuring a threshold voltage and a breakdown voltage, wherein a voltage of a switch signal is between the threshold voltage and the breakdown voltage since It was known in the art.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Onishi in view of Fan et al. (WO 2011095016 A1 and Fan hereinafter.).
Regarding claim 7, Onishi discloses all the features regarding claim 1 as indicated above. Onishi does not explicitly disclose the semiconductor device further comprising: a fourth transistor, wherein the second transistor and the fourth transistor are coupled in series between the third transistor and the first transistor.
However, Fan discloses [fig. 2] the semiconductor device further comprising: a fourth transistor [Q3], wherein the second transistor [Q2] and the fourth transistor are coupled in series between the third transistor [Q1] and the first transistor [Q4]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Onishi to include the semiconductor device further comprising: a fourth transistor, wherein the second transistor and the fourth transistor are coupled in series between the third transistor and the first transistor as taught by Fan to improve efficiency of a voltage limiting device.
Conclusion
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/JAMES G YEAMAN/Examiner, Art Unit 2842
/METASEBIA T RETEBO/Primary Examiner, Art Unit 2842