DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 6, 8-10, 13-16, 19, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iwahashi (US 5,448,517).
Regarding claim 1, fig. 19 and 29 of Iwahashi discloses a semiconductor device, comprising: a first transistor [MC4], configured to be conducted during a first enable period [of VG4]; and a second transistor [101], configured to be conducted during a second enable period [of Vin], wherein the first transistor and the second transistor are coupled in series, wherein the first enable period comprises a first delay period [before the on period of Vin], the second enable period [during the on period of Vin] and a second delay period [after the on period of Vin] arranged in sequence.
Regarding claim 2, fig. 19 and 29 of Iwahashi discloses a third transistor [MC1], wherein the third transistor is coupled between the first transistor and the second transistor, wherein the third transistor is conducted at least during the second enable period.
Regarding claim 5, fig. 19 and 29 of Iwahashi discloses wherein the third transistor remains being conducted during the first enable period (since VG1 is conducting while VG4 is conducting).
Regarding claim 6, fig. 19 and 29 of Iwahashi discloses wherein the third transistor is conducted during the second enable period, and the third transistor is switched off during the first delay period and the second delay period (since VG1 is off at the period before Vin is conducting and VG1 is off at the period after Vin is conducting).
Regarding claim 8, fig. 19 and 29 of Iwahashi discloses a fourth transistor [MC2], wherein the third transistor and the fourth transistor are coupled in series between the first transistor and the second transistor.
Regarding claim 9, fig. 19 and 29 of Iwahashi discloses wherein the first transistor, the second transistor and the third transistor are all P-type transistors or all N-type transistors.
Regarding claim 10, fig. 19 and 29 of Iwahashi discloses an amplifier (such as the sense amplifier of Iwahashi, or an amplifier where the memory of fig. 19 of Iwahashi is implemented), comprising: a first semiconductor device; and a second semiconductor device (col. 13, lines 39-42 describes a plurality of memory cells of the memory of fig. 19), coupled to the first semiconductor device, wherein the first semiconductor device and the second semiconductor device each comprises: a first transistor [MC4], configured to be conducted during a first enable period; a second transistor [101], configured to be conducted during a second enable period; and a third transistor [MC1], wherein the third transistor is coupled between the first transistor and the second transistor, wherein the first transistor is configured to receive an input signal, and the second transistor is configured to generate an output signal, wherein the first enable period comprises a first delay period [before the on period of Vin], the second enable period [during the on period of Vin] and a second delay period arranged in sequence, wherein the third transistor is conducted at least during the second enable period [after the on period of Vin].
Regarding claim 13, fig. 19 and 29 of Iwahashi discloses wherein the third transistor remains being conducted during the first enable period.
Regarding claim 14, fig. 19 and 29 of Iwahashi discloses wherein the third transistor is conducted during the second enable period, and the third transistor is switched off during the first delay period and the second delay period.
Regarding claim 15, fig. 19 and 29 of Iwahashi discloses a fourth transistor [MC2], wherein the third transistor and the fourth transistor are coupled in series between the first transistor and the second transistor.
Regarding claim 16, fig. 19 and 29 of Iwahashi discloses a biasing circuit, comprising: a semiconductor device, comprising a first transistor [MC4], a second transistor [101] and a third transistor [MC1], wherein the third transistor is coupled between the first transistor and the second transistor; a first voltage generation circuit [that generating VG4] (not shown), configured to output a first switch signal to control the first transistor to be conducted during a first enable period; a second voltage generation circuit [that generating Vin] (not shown), configured to output a second switch signal to control the second transistor to be conducted during a second enable period; and a third voltage generation circuit [that generating VG1] (not shown), configured to output a third switch signal to control the third transistor to be conducted at least during the second enable period, wherein the third voltage generation circuit and the third transistor form an negative feedback (based on feedback relating to access of the memory), wherein the first enable period comprises a first delay period [before the on period of Vin], the second enable period [during the on period of Vin] and a second delay period arranged in sequence, wherein the third transistor is conducted at least during the second enable period [after the on period of Vin].
Regarding claim 19, fig. 19 and 29 of Iwahashi discloses wherein the third transistor remains being conducted during the first enable period.
Regarding claim 20, fig. 19 and 29 of Iwahashi discloses wherein the third transistor is conducted during the second enable period, and the third transistor is switched off during the first delay period and the second delay period.
Allowable Subject Matter
Claims 3, 4, 7, 11, 12, 17, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Palubiak describes a semiconductor device with single-photon avalance diode pixels. Umeda describes a driver circuit. Iwahashi describes a memory cell of a nonvolatile semiconductor memory device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIBIN CHEN whose telephone number is (571)270-5768. The examiner can normally be reached 9:00am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SIBIN CHEN/Primary Examiner, Art Unit 2836
Prosecution Insights