DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 03/08/2026 have been fully considered but they are not persuasive.
The applicant contends, “The term "FEC decoder" is not a functional term, but rather refers to a well-established family of components, which are a standard part of many communication receivers and would have been familiar to any person of ordinary skill in the art. FEC decoders are widely available as off-the- shelf products for commercial purchase. Two examples among many are the "LogiCORE IP Reed-Solomon Decoder v8.0", part number DS862, offered since 2011 by Xilinx, Inc., and the REEDSDECO-E2-N1 Reed-Solomon Decoder offered since 2005 by Lattice Semiconductor Corp. Data sheets of these products are attached in an Appendix hereto.”
The Authoritative Dictionary of IEEE Dictionary of Standards Terms defines decoder as “a device or system that decodes data”. In particular, a system is not necessary hardware. In addition, the Applicant states in the paragraph starting in line 28 on page 6 to line 10 on page 7 of the Applicant’s specification that a “decoder may be implemented in a programmable processor, which is programming software to carry out the functions described herein the software may be downloaded to the process in electronic form over the network for example, or it may be alternatively or in addition be provided and/or stored on a non-transitory tangible medium”. So the Applicant’s own specification contradicts the assertion that a decoder is not a functional term. Furthermore, the Applicant’s arguments combined with what is taught in the Applicant’s specification confirms that the Applicant is using the term decoder is a placeholder for means plus function language.
The Applicant contends, “The above-mentioned Declaration by Lion Levi is submitted herewith precisely for this purpose. In the Declaration, Mr. Levi describes his experience in implementing the invention recited in claims 1 and 12. He notes the considerable reduction in the time needed for estimating Block Error Rate (BLER), as a direct result of using the claimed invention. Mr. Levi also explains the benefit of the reduced latency in a variety of practical real-life computing systems. Thus, the present claims reflect an improvement to the functioning of various computing systems. For at least this reason, the claims are also patent-eligible under Step 2A, Prong Two, specifically as defined in MPEP 2016.04 (d) (1).”
The Examiner disagrees and asserts that just because an abstract judicial exception saves time and it’s faster than the previous abstract judicial exception does not remove the footprint of the judicial exception. In addition, just because they can improve real-life computing systems does not tie them to real-life computing systems unless that language is in a claim and that language is supported by the specification. The claims themselves only recite an abstract judicial exception without any language that ties them to a apparatus or device such that when combined with that apparatus raises the level to a practical application. In addition, the specification has to teach the improvement to the apparatus or device in the specification because the Examiner reads the claims in light of the specification.
Specification
The amendment filed 03/08/2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: the Appendix to the Specification filed 03/08/2026.
Applicant is required to cancel the new matter in the reply to this Office Action.
Claim Interpretation
Claims 1 and 12 recite “Forward Error Correction (FEC) Decoder” as a generic placeholder for a functional means. The Applicant’s specification at lines 28-31 on page 6 states that the various elements in the claims can be software or a combination of hardware and software elements.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1 and 12 recite “Forward Error Correction (FEC) Decoder” as a generic placeholder for a functional means. The Applicant’s specification at lines 28-31 on page 6 states that the various elements in the claims can be software or a combination of hardware and software elements. However, the Applicant fails to disclose specific software and/or software steps and/or hardware to implement the FEC decoder. Note: when the applicant specifies multiple means for a placeholder, the Applicant must provide hardware or software elements for implementing the placeholder.
improvement.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3, 5-14 and 16-17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a mathematical method of estimating a distribution of erroneous code symbols over a set of codewords and using the distribution to estimate a block error rate associated with the set of codewords (pages 7-8 in the Applicant’s specification teaches the mathematical formulas and mathematical steps used to make these estimations) without significantly more. The claim(s) recite(s) an abstract mathematical algorithm by itself not including any structural element that when combined with the abstract algorithm raises the level to a practical application. This judicial exception is not integrated into a practical application because the claims only recite an abstract mathematical algorithm. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because an apparatus can be anything including a general-purpose computer which is insufficient to raise the level to a practical application.
The Examiner would like to point out that the FEC decoder can be software or a combination of hardware and software elements. Therefore, a “specific implementation” is not a requirement of the invention, but just one of many generic ways to run the algorithm. Hence, the claims are directed to a mathematical concept, not a specific technical improvement. Furthermore, Figure 1 the Applicant’s specification teaches that an RS decoder is a placeholder (a block chart is a diagram comprising block placeholders for functional elements); hence, the FEC decoder recited in the claims is just a generic structure (possibly software implemented on a general-purpose computer which is insufficient to remove the footprint of an abstract judicial exception. The Applicant’s amendment is an attempt to “backfill” a technical soul into a purely mathematical body without a specific description in the claims connecting it to how the FEC logic interacts with structural elements (if they exist).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20130061115 A1 directed to A method of adjusting a code word length and a generator polynomial, the method comprising: receiving a code word transmitted from a transmission system, and counting the code word; counting a bit error when a correctable error is detected; increasing an error correction level when an error bit rate exceeds an upper limit of the bit error rate, setting an upper limit of the error correction level to the error correction level when the error correction level exceeds the upper limit of the error correction level, and sending the error correction level to the transmission system, the error bit rate being a quotient of the number of the bit errors and the number of the code words; and decreasing the error correction level when the number of the code words exceeds a minimum number of receptions necessary for changing the error correction level and the bit error rate is less than a lower limit of the bit error rate, setting a lower limit of the error correction level to the error correction level when the error correction level is less than the lower limit of the error correction level, and sending the error correction level to the transmission system; and, is a good teaching reference.
US 20230343408 A1 directed to A method for determining storage subsystem read voltages, comprising: reading, by a storage subsystem read voltage determination system from a first storage subsystem at a plurality of different read voltage sets, data; generating, by the storage subsystem read voltage determination system for each of the plurality of read voltage sets, a respective bit error probability distribution of a number of bit errors per codeword provided by the data read from the first storage subsystem; generating, by the storage subsystem read voltage determination system, an error correction capability graph associated with an error correction code used by the first storage sub system; determining, by the respective storage subsystem read voltage determination system for each of the plurality of read voltage sets based on the bit error probability distributions and the error correction capability graph, a respective average codeword error rate; and identifying, by the storage subsystem read voltage determination system from the average codeword error rates, a first read voltage set that is included in the plurality of read voltage sets and for which a minimum average codeword error rate was determined; and, is a good teaching reference.
US 20250252027 A1 directed to A method comprising: performing, by a processor, a media scan on a portion of the memory device to obtain a metrics dataset comprising a plurality of data state metric values, wherein each data state metric value is associated with a respective codeword of a plurality of codewords stored on the portion of the memory device; generating, for the metrics dataset, a plurality of data state metric bins comprising a first set of bins having a first bin width and a second set of bins having a second bin width; associating a first data state metric value of the plurality of data state metric values with a first bin of first set of bins, and a second data state metric value of the plurality of data state metric values with a second bin of the second set of bins, wherein the first data state metric value exceeds the second data state metric value; and generating a histogram reflecting the data associated with the plurality of data state metric bins; and, is a good teaching reference.
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/JOSEPH D TORRES/Primary Examiner, Art Unit 2112 and