Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 2, 8-13, 15, 16, 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-7, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ueda (US 20180053735 A1) in view of Kim et al. (US 20210210441 A1) hereafter referred to as Kim
In regard to claim 1 Ueda teaches a [see Fig. 3] semiconductor package, comprising:
a substrate [“dielectric board 10”];
a radio frequency [“high-frequency integrated circuit element 21” it is radio frequency , see “The first antenna element 35 radiates radio waves upward with respect to the dielectric board 10 when being supplied with power from the high-frequency integrated circuit element 21”] integrated circuit (RFIC) attached to the substrate;
a molding compound [see Fig. 3 “sealing member 30 made of resin is disposed on the dielectric board 10”] encapsulating the RFIC; and
an antenna [“The first antenna element 35 radiates radio waves upward with respect to the dielectric board 10 when being supplied with power from the high-frequency integrated circuit element 21” “transmission line 38 provided in the dielectric board 10”] formed on the molding compound and coupled to the RFIC.
but does not teach at least one semiconductor die attached to the substrate and coupled to the RFIC via one or more signal lines; that the molding compound is also encapsulating the semiconductor die.
See other elements sealed with 21 “the high-frequency integrated circuit element 21 and the passive component 22 are sealed by the sealing member 30” .
See Kim Fig. 4D see “An RFIC 300 and a PMIC 600 are mounted on a lower surface of the first connection member 100, and are encapsulated by an encapsulant layer 180” “Referring to FIGS. 2A and 2B, radio-frequency modules 10d and 10e may further include a power management integrated circuit (PMIC) 600. The PMIC 600 may supply power to an RFIC 300” “a first power wiring 161 electrically connected between the first PM connection terminal 611 of the PMIC 600 and the power connection terminal 316 of the RFIC 300”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Ueda to include at least one semiconductor die attached to the substrate and coupled to the RFIC via one or more signal lines; that the molding compound is also encapsulating the semiconductor die.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to provide clean regulated power using power management to the high-frequency integrated circuit element 21.
In regard to claim 3 Ueda and Kim as combined teaches wherein the antenna or the semiconductor die is coupled to the RFIC via [see Ueda Fig. 3 “transmission line 38 provided in the dielectric board 10”] one or more redistribution layers of the semiconductor package.
In regard to claim 4 Ueda and Kim as combined teaches wherein the molding compound laterally extends beyond [see Ueda Fig. 3] the RFIC and the antenna is formed on the molding compound laterally [see Ueda Fig. 3] adjacent to the RFIC.
In regard to claim 5 Ueda and Kim as combined teaches further comprising a ground plane [see Ueda Fig. 3 “Ground planes 11 are provided to a dielectric board 10”] formed in the molding compound as a counterpoise to the antenna.
In regard to claim 6 Ueda and Kim as combined teaches wherein the antenna is coupled to the ground plane by means of at least one shorting via or the antenna is coupled to [see Ueda Fig. 3 “Ground planes 11 are provided to a dielectric board 10” “The first antenna element 35 radiates radio waves upward with respect to the dielectric board 10 when being supplied with power from the high-frequency integrated circuit element 21” “transmission line 38 provided in the dielectric board 10”] the RFIC by means of a feeding via extending from or through the ground plane.
In regard to claim 7 Ueda and Kim as combined teaches wherein the antenna comprises a floating via [“conductor bar 37 for connecting the first antenna element 35 to the high-frequency integrated circuit element 21 penetrates the dielectric layer 32, the shield film 27, and the sealing member 30 in the thickness direction”] extending from the antenna towards the ground plane.
In regard to claim 14 Ueda and Kim as combined teaches wherein the ground plane comprises a cutout [see Ueda Fig. 3 “Ground planes 11 are provided to a dielectric board 10” “The first antenna element 35 radiates radio waves upward with respect to the dielectric board 10 when being supplied with power from the high-frequency integrated circuit element 21” “transmission line 38 provided in the dielectric board 10”] portion underneath the antenna.
Claim(s) 17, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20210011069 A1) hereafter referred to as Chen in view of Kato (US 20170047634 A1)
In regard to claim 17 Chen teaches a wireless communication [see Fig. 1 “An integrated circuit with antenna in package (AiP IC) testing apparatus is provided”] system comprising:
a substrate [“carrier board 11”];
a first semiconductor package [“The AiP IC 10 can emit a wireless signal, such as a millimeter wave (mmWAVE) RF signal”] mounted on the substrate, wherein the first semiconductor package comprises: a first radio frequency integrated [i.e. “AiP IC 10” emits RF] circuit (RFIC), and a first antenna [see AiP is “integrated circuit with antenna in package (AiP IC)”] coupled to the first RFIC,
a second antenna [“receiving antenna circuit board 16”] and further teaches that the antenna wirelessly communicate with each other “As shown in FIG. 1 and FIG. 2, the receiving antenna circuit board 16 is disposed at an angle on the soft board 13, and the receiving antenna circuit board 16 is adjacent to the test socket 12”,
but does not teach a first molding compound encapsulating the first RFIC, and that the first antenna formed on a surface of the first molding compound;
a second semiconductor package mounted on the substrate, wherein the second semiconductor package comprises: a second RFIC, a second molding compound encapsulating the second RFIC, and a second antenna formed on a surface of the second molding compound and coupled to the second RFIC,
wherein the first and the second semiconductor packages are configured to wirelessly communicate with each other using the first RFIC with the first antenna and the second RFIC with the second antenna.
See Kato teaches see Fig. 6 “The present invention relates to a wireless IC device for use in, for example, a near field wireless communication device, such as a radio frequency identification (RFID) tag, and also relates to a molded resin article including the wireless IC device and a method for manufacturing a coil antenna” “FIG. 6 is sectional view illustrating successive manufacturing steps of a non-limiting example of a method of manufacturing the wireless IC device 103” “the first-principal-surface-side conductor patterns, lands to mount the RFIC element (power supply terminals and NC terminals), lands to mount the chip capacitors, and a routing pattern to connect these lands to each other are formed on the first principal surface PS1 of the first substrate 1. In addition, the second-principal-surface-side conductor patterns are formed on the second principal surface PS2 of the first substrate 1” “as illustrated in part (2) of FIG. 6, the RFIC element 61, the chip capacitors 62 and 63, and the metal posts (30A and 40A, etc.) are mounted on the first substrate 1” “as illustrated in part (3) of FIG. 6, the resin member 70 is formed so that the height thereof is the same as that of the metal posts (30A and 40A, etc.)” “as illustrated in part (4) of FIG. 6, the connection conductors (50A, etc.) are formed on the surface of the resin member 70” “The first metal posts 30A to 30F, the second metal posts 40A to 40F, the connection conductors 50A to 50F, the first-principal-surface-side conductor patterns 10A to 10L, and the second-principal-surface-side conductor patterns 20A to 20E define a six-turn helical coil antenna” “Preferably, the RFIC element includes, in addition to an input-output terminal for a radio signal that is connected to the coil antenna, a digital signal terminal (for example, an I.sup.2C bus terminal or a control terminal) connected to an external digital circuit, and a terminal that is electrically connected to the digital signal terminal and connected to the external digital circuit is provided on the printed wiring board”. See that the coil of Kato “the frequency band of the coil antenna (the RFID tag) is not limited to HF-band, and may instead be LF-band, UHF-band, or SHF-band”.
However see that primary reference Chen knows how to make a millimeter wave (mmWAVE) RF antenna.
Thus it would be obvious to a person of ordinary skill in the art to use packages like Kato with molded RFIC and the coupled antenna on molding as package 10 and as antenna 16 to perform testing using the test structure of Chen.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Chen to include a first molding compound encapsulating the first RFIC, and that the first antenna formed on a surface of the first molding compound; a second semiconductor package mounted on the substrate, wherein the second semiconductor package comprises: a second RFIC, a second molding compound encapsulating the second RFIC, and a second antenna formed on a surface of the second molding compound and coupled to the second RFIC, wherein the first and the second semiconductor packages are configured to wirelessly communicate with each other using the first RFIC with the first antenna and the second RFIC with the second antenna.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is use the test structure of Chen to perform more work by testing a wide variety of RF emitter/receiver packages and that the package of Kato is simple and easy to use to match RF emitter/receiver.
In regard to claim 18 Chen and Kato as combined teaches wherein the first and the second semiconductor packages are configured to wirelessly exchange [see combination, see that Kato is a testing platform, see that use packages like Kato with molded RFIC and the coupled antenna on molding as package 10 and as antenna 16 to perform testing] test or debug signals using the first RFIC with the first antenna and the second RFIC with the second antenna.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ueda (US 20180053735 A1) in view of Kim et al. (US 20210210441 A1) hereafter referred to as Kim
In regard to claim 20 Ueda teaches a [see Fig. 3] wireless communication method, comprising:
providing a radio frequency [“high-frequency integrated circuit element 21” it is radio frequency , see “The first antenna element 35 radiates radio waves upward with respect to the dielectric board 10 when being supplied with power from the high-frequency integrated circuit element 21”] integrated circuit (RFIC) die on a package substrate [“dielectric board 10”];
encapsulating [see Fig. 3 “sealing member 30 made of resin is disposed on the dielectric board 10”] the RFIC die using a molding compound;
forming an antenna [“The first antenna element 35 radiates radio waves upward with respect to the dielectric board 10 when being supplied with power from the high-frequency integrated circuit element 21”] in or on the molding compound; and
coupling [“transmission line 38 provided in the dielectric board 10”] the antenna to the RFIC die,
but does not teach providing at least one further semiconductor die on the package substrate; coupling the at least one further semiconductor die to the RFIC die via one or more signal lines in the package; and that the encapsulating includes the least one further semiconductor die .
See other elements sealed with 21 “the high-frequency integrated circuit element 21 and the passive component 22 are sealed by the sealing member 30” .
See Kim Fig. 4D see “An RFIC 300 and a PMIC 600 are mounted on a lower surface of the first connection member 100, and are encapsulated by an encapsulant layer 180” “Referring to FIGS. 2A and 2B, radio-frequency modules 10d and 10e may further include a power management integrated circuit (PMIC) 600. The PMIC 600 may supply power to an RFIC 300” “a first power wiring 161 electrically connected between the first PM connection terminal 611 of the PMIC 600 and the power connection terminal 316 of the RFIC 300”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Ueda to include providing at least one further semiconductor die on the package substrate; coupling the at least one further semiconductor die to the RFIC die via one or more signal lines in the package; and that the encapsulating includes the least one further semiconductor die .
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to provide clean regulated power using power management to the high-frequency integrated circuit element 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt D Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
