CTNF 18/817,299 CTNF 83953 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statements (IDS) submitted are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 2-5 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claims 2-5 , the claims each recite the limitation of “the digital filtering process” however parent claim 1 discloses “a plurality of digital filtering processes.” It is therefore unclear which of the processes is being referred to of if an additional process is being introduced. For the purpose of examination, it will be interpreted as one of the digital filtering processes or similar. Regarding claim 9 , the claim recites the limitation of “a signal processing circuit that performs a digital filtering process on a digital signal output from the A/D conversion circuit.” It is unclear if this is part of the method as a step being performed, or an intended use of the signal processing circuit. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 3, 4 and 6-9 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Nakajima US 2015/0160011 . Regarding claim 1 , Nakajima teaches a circuit device as seen in fig. 2, comprising an A/D conversion circuit 100 that A/D converts a signal output from a sensor element 10; an interface circuit (paragraph 0103 describes a register connected to storage unit 116) that receives filter setting data (via storage unit 116, paragraph 0077) that determines a characteristic of each of a plurality of digital filtering processes (information on the filter coefficients, paragraph 0103); a storage circuit 116 that stores the filter setting data; and a signal processing circuit 110 that sequentially performs each of the plurality of digital filtering processes with characteristics determined by the filter setting data on a digital signal output from the A/D conversion circuit (filter units 112 and 114 receive the A/D converted signal from circuit 100 and the filter settings from storage unit 116). Regarding claims 3 and 4 , Nakajima teaches the filter as performing a notch filtering process (band elimination filter, 114) and a low pass filter filtering process (low pass filter 112) as claimed. Regarding claim 6 , Nakajima teaches a drive circuit 30 that vibrates the sensor element 10 at a drive frequency and a detection circuit 60 that acquires a signal of a detection frequency from the sensor element, the signal processing circuit performing a notch filtering process of attenuating a component of a detuned frequency that is a difference between the drive frequency and the detection frequency and the plurality of digital filtering processes (paragraph 0012). Regarding claim 7 , Nakajima teaches the filter as being a low pass filter 112 which when combined with the storage circuit would function in the claimed manner to set a cutoff frequency designated by a user (paragraph 0018). The processing circuit then would be capable of performing the low-pass filtering process. Regarding claim 8 , the system of Nakajima is configured in a manner which stores the sampling frequency since it is used in the calculation of the notch filter (paragraph 0097). Since the system is capable of storing the data, the step of overwriting the data by filter setting does not change the structural limitations of the claim and therefore the Nakajima reference reads on the structural elements and the claim in its entirety. Regarding claim 9 , Nakajima teaches a method of setting a circuit device including an A/D conversion circuit 100 that A/D converts a signal output from a sensor element 10, an interface circuit (paragraph 0103 describes a register connected to storage unit 116), a storage circuit 116, and a signal processing circuit 110 that performs a digital filtering process on a digital signal output from the A/D conversion circuit, the method comprising: inputting filter setting data (via storage unit 116, paragraph 0077) that determines a characteristic of each of a plurality of digital filtering processes into the interface circuit (filter units 112 and 114 receive the A/D converted signal from circuit 100 and the filter settings from storage unit 116), and storing the filter setting data in the storage circuit; and causing the signal processing circuit to sequentially perform each of the plurality of digital filtering processes (the filters 112, 114 are located sequentially) with characteristics determined by the filter setting on the digital signal output from the A/D conversion circuit data (paragraph 0026 discloses filter setting data which is applied to the output digital signal) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim (s) 2 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakajima as applied to claim 1 above and further in view of and Bickford US 2018/0292470 . Regarding claims 2 and 5 , Nakajima teaches the claimed invention including a notch filtering process (band elimination filter, 114) and a low pass filter filtering process (low pass filter 112) but does not explicitly disclose the bandpass and high-pass filters claimed. Bickford teaches a sensor element which includes processing circuitry 600 including a high pass filter and a bandpass filter (paragraphs 0077-0078). It would have been obvious to one of ordinary skill in the art at the time of filing to have combined the teachings of Bickford with those of Nakajima to provide any desired form of filtering for the signal to narrow the band of frequencies to extract the desired signals more effectively. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark A. Shabman whose telephone number is (571)272-8589. The examiner can normally be reached M-F 8:00-4:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Laura Martin can be reached at 571-272-2160. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARK A SHABMAN/ Primary Examiner, Art Unit 2855 Application/Control Number: 18/817,299 Page 2 Art Unit: 2855 Application/Control Number: 18/817,299 Page 3 Art Unit: 2855 Application/Control Number: 18/817,299 Page 4 Art Unit: 2855 Application/Control Number: 18/817,299 Page 5 Art Unit: 2855 Application/Control Number: 18/817,299 Page 6 Art Unit: 2855 Application/Control Number: 18/817,299 Page 7 Art Unit: 2855
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