DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 10 is objected to because of the following informalities:
Claim 10 appears to recite what the Examiner assumes is a grammatical error. In claim 10, the phrase “a width in the first direction that is is constant” should read “a width in the first direction that is constant”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “substantially perpendicular” in claims 1 and 8 is a relative term which renders the claim indefinite. The term “substantially perpendicular” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
For purposes of examination, the Examiner will interpret “substantially perpendicular” as “perpendicular”
The term “is substantially equal to” in claims 2, 3, 7, 8, 10, 13, and 15 is a relative term which renders the claim indefinite. The term “is substantially equal to” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
For purposes of examination, the Examiner will interpret “is substantially equal to” as “may have a difference in value of up to 10% when compared to” which is similar to the meaning of “substantially the same size” as defined in the specification in [0035].
Claim 17 recites the limitation "the second direction" in line 17 on page 5. There is insufficient antecedent basis for this limitation in the claim.
For purposes of examination, the Examiner will interpret “the second direction” as “a second direction”
The balance of claims are rejected for being dependent upon an already rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over OH (US 20230112006 A1) in view of KAGAWA (US 20160233264 A1).
Claim 1, OH discloses a semiconductor chip comprising:
a semiconductor substrate including a first surface and a second surface that is opposite to the first surface (second semiconductor substrate 210, hereinafter semiconductor substrate 210, shares a first surface with a bonding insulation material layer 300a and shares a second surface with second inter-wiring insulation layer 236, Fig. 13A);
a through-via disposed in the semiconductor substrate 210 (through via portion 314D, hereinafter through-via 314D, is disposed in the semiconductor substrate 210, [0034], Fig. 13B);
a first bonding pad disposed on the first surface of the semiconductor substrate 210 and electrically connected to the through-via 314D (pad portion 312D, hereinafter first bonding pad 312D is disposed on the first surface of the semiconductor substrate 210 and electrically connected to the through-via 314D, Fig. 13B; bonding pad 310 comprises first bonding pad 312D making first bonding pad 312D a bonding pad, [0033]);
a first dummy pad disposed on the first surface of the semiconductor substrate 210 and insulated from the through-via 314D (rear thermal pad portion 344D, hereinafter first dummy pad 344D, is disposed on the first surface of the semiconductor substrate 210 and insulated from the through-via 314D, Fig. 13B); and
a second bonding pad disposed on the second surface of the semiconductor substrate 210 and electrically connected to the through-via 314D (second chip pad 250, hereinafter second bonding pad 250 is disposed on the second surface of the semiconductor substrate 210 and electrically connected to the through-via 314D, Figs. 13A/13B),
wherein a first maximum width of the first bonding pad 312D is greater than a second maximum width in a first direction of the first dummy pad 344D (the first horizontal width W1 of the first bonding pad 312D, hereinafter first maximum width W1 of the first bonding pad 312D, is greater than the second horizontal width W2 of the first dummy pad 344D, hereinafter second maximum width W2 of the first dummy pad 344D, in the X direction, hereinafter first direction, [0049], Fig. 13B), and
wherein the first direction is perpendicular to a second direction (first direction is perpendicular to Y-direction, hereinafter second direction, Figs. 13A/13B).
OH does not explicitly disclose wherein a first maximum width of the first bonding pad is smaller than a third maximum width in the second direction of the first dummy pad.
However, KAGAWA teaches changing the shape of a Cu pad on its bonding surface to prevent dishing from occurring ([0092]) during chemical-mechanical polishing (CMP, [0091]).
The first maximum width of the first bonding pad and the third maximum width in a second direction of a first dummy pad are result effective variables as one would have chosen them to be shaped so that dishing would be prevented during CMP ([0092]) and so that part of the bonding surface could be more firmly protected ([0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by OH with the teaching disclosed by KAGAWA as it would merely result in an optimization of result effective variables.
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OH Figure 13A
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OH Figure 13B
Claim 4, The combination of OH and KAGAWA discloses the semiconductor chip of claim 1.
OH further discloses wherein the second maximum width W2 in the first direction of the first dummy pad 344D is greater than a fourth maximum width of the through-via 314D (the second maximum width W2 in the first direction of the first dummy pad 344D is greater than the fourth horizontal width W4, hereinafter fourth maximum width W4, of the through-via 314D, [0050], Fig. 13B).
Claim 6, The combination of OH and KAGAWA discloses the semiconductor chip of claim 1.
OH further discloses the semiconductor chip of claim 1, further comprising a second dummy pad disposed on the second surface of the semiconductor substrate 210 and insulated from the through-via 314D (front thermal pad portion 342D, hereinafter second dummy pad 342D, is disposed on the second surface of the semiconductor substrate 210 and insulated from the through-via 314D, Fig. 13B).
Claims 2-3, 5, 7-15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over OH in view of KAGAWA further in view of CHUNG (US 20230154910 A1).
Claim 2, The combination of OH and KAGAWA teaches the semiconductor chip of claim 1.
The combination of OH and KAGAWA does not explicitly teach wherein the first dummy pad may include an area having a width in the first direction that is constant and may have a difference in value of up to 10% when compared to the second maximum width.
However CHUNG discloses wherein a first dummy pad may include an area having a width in a first direction that is constant and may have a difference in value of up to 10% when compared to a second maximum width of the first dummy pad (first dummy pad DP1 has a width w3b in the X direction that remains constant in the Y direction, Fig. 4C).
The width of the first dummy pad in the first direction and the second maximum width are result effective variables as one would have chosen them to be shaped so that dishing would be prevented during CMP (KAGAWA, [0092]) and so that part of the bonding surface could be more firmly protected (KAGAWA, [0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by OH with the teaching disclosed by KAGAWA and limitation disclosed by CHUNG as it would merely result in an optimization of result effective variables.
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CHUNG Fig. 4C
Claim 3, The combination of OH and KAGAWA teaches the semiconductor chip of claim 1.
The combination of OH and KAGAWA does not explicitly teach wherein a size of an area of the first bonding pad may have a difference in value of up to 10% when compared to a size of an area of the first dummy pad.
However CHUNG discloses wherein a size of an area of a first bonding pad may have a difference in value of up to 10% when compared to a size of an area of a first dummy pad (the planar area of the first dummy pad DP1 and first connection pad BP1 may be the same, [0051]).
The size of an area of a first bonding pad and the size of an area of a first dummy pad are result effective variables as one would have chosen them to be shaped so that dishing would be prevented during CMP (KAGAWA, [0092]) and so that part of the bonding surface could be more firmly protected (KAGAWA, [0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by OH with the teaching disclosed by KAGAWA and limitation disclosed by CHUNG as it would merely result in an optimization of result effective variables.
Claim 5, The combination of OH and KAGAWA teaches the semiconductor chip of claim 1.
The combination of OH and KAGAWA does not explicitly teach the semiconductor chip of claim 1, further comprising a semiconductor device layer disposed on the second surface of the semiconductor substrate and electrically connected to the through-via.
However, CHUNG discloses a semiconductor device layer disposed on a second surface of a semiconductor substrate and electrically connected to a through-via (circuit layer 120 is disposed on front surface FR of semiconductor substrate 110 and surrounds elements 115 constituting an integrated circuit and are electrically connected to interconnect structure 125 which is further electrically connected to via plug 145, [0032], Fig. 1B)
As suggested in CHUNG in [0032], the individual elements may include FETs such as planar FETs or FinFETs, memory devices such as a flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, FeRAM, and RRAM, logic devices such as AND, OR, NOT, and various active devices and/or passive devices such as system LSI, CIS, and MEMS. Therefore, the addition of the semiconductor device layer would allow a larger variety and quantity of devices to be incorporated in the overall device design and open the overall device to a wider variety of applications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention taught by the combination of OH and KAGAWA with the semiconductor device layer of CHUNG in order to allow a larger variety and quantity of devices to be incorporated in the overall device design and open the overall device to a wider variety of applications.
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CHUNG Fig. 1B
Claim 7, The combination of OH and KAGAWA teaches the semiconductor chip of claim 6.
The combination of OH and KAGAWA does not explicitly teach wherein a size of an area of the second bonding pad may have a difference in value of up to 10% when compared to a size of an area of the second dummy pad, and a shape of the second bonding pad is different from a shape of the second dummy pad.
However, CHUNG discloses wherein a size of an area of a second bonding pad may have a difference in value of up to 10% when compared to a size of an area of a second dummy pad, and a shape of the second bonding pad is different from a shape of the second dummy pad (the planar area of the first dummy pad DP1 and first connection pad BP1 may be the same, [0051]; first connection pad BP1 has a different shape than the first dummy pad DP1, Fig. 4C).
The size of an area of a second bonding pad, size of an area of a second dummy pad, shape of the second bonding pad, and shape of the second dummy pad are result effective variables as one would have chosen them to be shaped so that dishing would be prevented during CMP (KAGAWA, [0092]) and so that part of the bonding surface could be more firmly protected (KAGAWA, [0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by OH with the teaching disclosed by KAGAWA and limitation disclosed by CHUNG as it would merely result in an optimization of result effective variables.
Claim 8, OH discloses a semiconductor package comprising:
a first semiconductor chip (first semiconductor chip 100, Fig. 13A) including:
a first bonding insulating film (the combination of rear insulation material portion 304D and bonding insulation material portion 306D, hereinafter first bonding insulating film 304/306D, is a part of bonding insulation material layer 300a, [0119], Fig. 13B); and
a first bonding pad and a first dummy pad disposed in the first bonding insulating film 304/306D (pad portion 312D, hereinafter first bonding pad 312D, and rear thermal pad portion 344D, hereinafter first dummy pad 344D, are disposed in the first bonding insulating film 304/306D, Fig. 13B; bonding pad 310 comprises first bonding pad 312D making first bonding pad 312D a bonding pad, [0033]); and
a second semiconductor chip (second semiconductor chip 200, Fig. 13A) including:
a second bonding insulating film disposed on the first bonding insulating film 304/306D (the combination of second inter-wiring insulation layer 236 and front insulation material portion 302D, hereinafter second bonding insulation film 236/302D, is disposed on the first bonding insulating film 304/306D, Fig. 13B); and
a second bonding pad disposed in the second bonding insulating film 236/302D and in contact with the first bonding pad 344D (second chip pad 250, hereinafter second bonding pad 250 is in contact with the first bonding pad 344D, Figs. 13A/13B; a lower surface of second bonding pad 250 may be covered by the second bonding insulating film 236/302D, [0120]),
wherein a first maximum width of the first bonding pad 312D is different from each of a
second maximum width in a first direction of the first dummy pad 344D (the first horizontal width W1 of the first bonding pad 312D, hereinafter first maximum width W1 of the first bonding pad 312D, is greater than the second horizontal width W2 of the first dummy pad 344D, hereinafter second maximum width W2 of the first dummy pad 344D, in the X direction, hereinafter first direction, [0049], Fig. 13B), and
wherein the first direction is perpendicular to a second direction (first direction is perpendicular to Y-direction, hereinafter second direction, Figs. 13A/13B).
OH does not explicitly disclose wherein a size of an area of the first bonding pad may have a difference in value of up to 10% when compared to a size of an area of the first dummy pad, and
wherein a first maximum width of the first bonding pad is different from a third maximum width in a second direction of the first dummy pad.
However CHUNG discloses wherein a size of an area of a first bonding pad may have a difference in value of up to 10% when compared to a size of an area of a first dummy pad (the planar area of the first dummy pad DP1 and first connection pad BP1 may be the same, [0051]).
The size of an area of a first bonding pad and the size of an area of a first dummy pad are result effective variables as one would have chosen them to be shaped so that dishing would be prevented during CMP (KAGAWA, [0092]) and so that part of the bonding surface could be more firmly protected (KAGAWA, [0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by OH with the teaching disclosed by KAGAWA and limitation disclosed by CHUNG as it would merely result in an optimization of result effective variables.
The combination of OH and CHUNG does not explicitly teach wherein a first maximum width of the first bonding pad is different from a third maximum width in a second direction of the first dummy pad.
However, KAGAWA teaches changing the shape of a Cu pad on its bonding surface to prevent dishing from occurring ([0092]) during chemical-mechanical polishing (CMP, [0091]).
The first maximum width of the first bonding pad and the third maximum width in a second direction of a first dummy pad are result effective variables as one would have chosen them to be shaped so that dishing would be prevented during CMP ([0092]) and so that part of the bonding surface could be more firmly protected ([0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by OH with the teaching disclosed by KAGAWA as it would merely result in an optimization of result effective variables.
Claim 9, The combination of OH, KAGAWA, and CHUNG teaches the semiconductor package of claim 8.
OH further discloses wherein the first maximum width W1 of the first bonding pad 312D is greater than the second maximum width W2 of the first dummy pad 344D (the first maximum width W1 of the first bonding pad 312D, is greater than the second maximum width W2 of the first dummy pad 344D, in the first direction, [0049], Fig. 13B).
OH does not explicitly disclose wherein the first maximum width of the first bonding pad is smaller than the third maximum width of the first dummy pad.
However, KAGAWA teaches changing the shape of a Cu pad on its bonding surface to prevent dishing from occurring ([0092]) during chemical-mechanical polishing (CMP, [0091]).
The first maximum width of the first bonding pad and the third maximum width of a first dummy pad are result effective variables as one would have chosen them to be shaped so that dishing would be prevented during CMP ([0092]) and so that part of the bonding surface could be more firmly protected ([0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by OH with the teaching disclosed by KAGAWA as it would merely result in an optimization of result effective variables.
Claim 10, The combination of OH, KAGAWA, and CHUNG teaches the semiconductor package of claim 8.
The combination of OH, KAGAWA, and CHUNG does not explicitly teach wherein the first dummy pad may include an area having a width in the first direction that is constant along the second direction and may have a difference in value of up to 10% when compared to the second maximum width.
However CHUNG discloses wherein a first dummy pad may include an area having a width in the first direction that is constant along a second direction and may have a difference in value of up to 10% when compared to a second maximum width (first dummy pad DP1 has a width w3b in the X direction that remains constant in the Y direction, Fig. 4C).
The width of the first dummy pad in the first direction and the second maximum width are result effective variables as one would have chosen them to be shaped so that dishing would be prevented during CMP (KAGAWA, [0092]) and so that part of the bonding surface could be more firmly protected (KAGAWA, [0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by OH with the teaching disclosed by KAGAWA and limitation disclosed by CHUNG as it would merely result in an optimization of result effective variables.
Claim 11, The combination of OH, KAGAWA, and CHUNG teaches the semiconductor package of claim 8.
The combination of OH, KAGAWA, and CHUNG does not explicitly teach wherein the first bonding pad has a circular shape, and the first dummy pad has an elliptical shape.
However, CHUNG discloses wherein a first bonding pad has a circular shape, and a first dummy pad has an elliptical shape (first connection pad BP1 has a circular shape, Fig. 4C; first dummy pad DP1 may by an ellipse, [0051]).
As taught in KAGAWA, changing the shape of a Cu pad on its bonding surface can prevent dishing from occurring ([0092]) during chemical-mechanical polishing (CMP, [0091]) and allow part of the bonding surface to be more firmly protected ([0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by OH with the teaching disclosed by KAGAWA and limitation disclosed by CHUNG in order to prevent dishing from occurring during chemical-mechanical polishing and allow part of the bonding surface to be more firmly protected.
Claim 12, The combination of OH, KAGAWA, and CHUNG teaches the semiconductor package of claim 8.
OH further discloses wherein the first dummy pad 344D is in contact with the second bonding insulating film 236/302D (first dummy pad 344D is in contact with second dummy pad 342D which is further in contact with second bonding insulating film 236/302D, therefore first dummy pad 344D is in contact with second bonding insulating film 236/302D, Fig. 13B).
Claim 13, The combination of OH, KAGAWA, and CHUNG teaches the semiconductor package of claim 8.
OH further discloses wherein the second semiconductor chip 200 further includes a second dummy pad disposed in the second bonding insulating film 236/302D (second semiconductor chip 200 includes front thermal pad portion 342D, hereinafter second dummy pad 342D, disposed in the second bonding insulating film 236/302D, Figs. 13A/13B).
OH does not explicitly disclose wherein a size of an area of the second bonding pad may have a difference in value of up to 10% when compared to a size of an area of the second dummy pad, wherein the second bonding pad has a circular shape, and the second dummy pad has an elliptical shape.
However CHUNG discloses wherein a size of an area of a second bonding pad may have a difference in value of up to 10% when compared to a size of an area of a second dummy pad, wherein the second bonding pad has a circular shape, and the second dummy pad has an elliptical shape (the planar area of the first dummy pad DP1 and first connection pad BP1 may be the same, [0051]; first connection pad BP1 has a circular shape, Fig. 4C; first dummy pad DP1 may by an ellipse, [0051]).
As taught in KAGAWA, changing the shape of a Cu pad on its bonding surface can prevent dishing from occurring ([0092]) during chemical-mechanical polishing (CMP, [0091]) and allow part of the bonding surface to be more firmly protected ([0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by OH with the teaching disclosed by KAGAWA and limitation disclosed by CHUNG in order to prevent dishing from occurring during chemical-mechanical polishing and allow part of the bonding surface to be more firmly protected.
In addition, the size of an area of a second bonding pad and the size of an area of a second dummy pad are result effective variables as one would have chosen them to be shaped so that dishing would be prevented during CMP (KAGAWA, [0092]) and so that part of the bonding surface could be more firmly protected (KAGAWA, [0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by OH with the teaching disclosed by KAGAWA and limitation disclosed by CHUNG as it would merely result in an optimization of result effective variables.
Claim 14, The combination of OH, KAGAWA, and CHUNG teaches the semiconductor package of claim 13.
OH further discloses wherein the second dummy pad 342D is in contact with the first dummy pad 344D (second dummy pad 342D is in contact with the first dummy pad 344D, Fig. 13B).
Claim 15, OH discloses a semiconductor package comprising:
a first semiconductor chip (first semiconductor chip 100, Fig. 13A); and
a chip stack including a plurality of second semiconductor chips that are stacked on the first semiconductor chip 100 (plurality of second semiconductor chips 200 are stacked on the first semiconductor chip 100, Fig. 13A),
wherein each of the plurality of second semiconductor chips 200 includes:
a semiconductor substrate including a first surface and a second surface that is opposite to the first surface (the second semiconductor chip 200 may include the second semiconductor substrate 210, hereinafter semiconductor substrate 210, including an active surface, hereinafter second surface, and an inactive surface, hereinafter first surface, opposite to each other, [0023]);
a through-via extending through the semiconductor substrate 210 (through via portion 314D, hereinafter through-via 314D, is disposed in the semiconductor substrate 210, [0034], Fig. 13B);
a first bonding insulating film disposed on the first surface of the semiconductor substrate 210 (the combination of rear insulation material portion 304D and bonding insulation material portion 306D, hereinafter first bonding insulating film 304/306D, is a part of bonding insulation material layer 300a, and is disposed on the first surface of the semiconductor substrate 210, [0119], Fig. 13B);
a first bonding pad disposed in the first bonding insulating film 304/306D and electrically connected to the through-via 314D (pad portion 312D, hereinafter first bonding pad 312D, is disposed in the first bonding insulating film 304/306D, Fig. 13B; bonding pad 310 comprises first bonding pad 312D making first bonding pad 312D a bonding pad, [0033]);
a first dummy pad disposed in the first bonding insulating film 304/306D and insulated from the through-via 314D (rear thermal pad portion 344D, hereinafter first dummy pad 344D, is disposed in the first bonding insulating film 304/306D and insulated from the through-via 314D, Fig. 13B);
a second bonding insulating film disposed on the second surface of the semiconductor substrate 210 (the combination of second inter-wiring insulation layer 236 and front insulation material portion 302D, hereinafter second bonding insulation film 236/302D, is disposed on the second surface of the semiconductor substrate 210, Fig. 13B); and
a second bonding pad disposed in the second bonding insulating film 236/302D and electrically connected to the through-via 314D (second chip pad 250, hereinafter second bonding pad 250, may be electrically connected to through-via 314D, [0024]; a lower surface of second bonding pad 250 may be covered by the second bonding insulating film 236/302D, [0120]),
wherein the first bonding pad 312D of a first second semiconductor chip of the plurality of second semiconductor chips 200 and the second bonding pad 250 of a second second semiconductor chip of the plurality of second semiconductor chips 200 are adjacent to each other and are in contact with each other (bonding pad 312D of a first second semiconductor chip 200 is in contact with second bonding pad 250 of a second semiconductor chip 200, Figs. 13A/13B), and
wherein the first dummy pad 344D includes a portion that has a width in a first direction that is smaller than a first maximum width of the first bonding pad 312D (the first horizontal width W1 of the first bonding pad 312D, hereinafter first maximum width W1 of the first bonding pad 312D, is greater than the second horizontal width W2 of the first dummy pad 344D, hereinafter second maximum width W2 of the first dummy pad 344D, in the X direction, hereinafter first direction, [0049], Fig. 13B).
OH does not explicitly disclose wherein a size of an area of the first bonding pad may have a difference in value of up to 10% when compared to a size of an area of the first dummy pad, and
wherein the first dummy pad includes a portion that has a width in a first direction that may have a difference in value of up to 10% when compared to a second maximum width of the first dummy pad.
However CHUNG discloses wherein a size of an area of the first bonding pad may have a difference in value of up to 10% when compared to a size of an area of the first dummy pad (the planar area of the first dummy pad DP1 and first connection pad BP1 may be the same, [0051]), and
wherein the first dummy pad includes a portion that has a width in a first direction that may have a difference in value of up to 10% when compared to a second maximum width of the first dummy pad (first dummy pad DP1 has a width w3b in the X direction that remains constant in the Y direction, therefore any width chosen in the X direction on the Y axis for first dummy pad DP1 will be the same as width w3b, Fig. 4C).
The size of an area of a first bonding pad, size of an area of a first dummy pad, the width of the first dummy pad in a first direction, and the second maximum width of the first dummy pad are result effective variables as one would have chosen them to be shaped so that dishing would be prevented during CMP (KAGAWA, [0092]) and so that part of the bonding surface could be more firmly protected (KAGAWA, [0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by OH with the teaching disclosed by KAGAWA and limitation disclosed by CHUNG as it would merely result in an optimization of result effective variables.
Claim 18, The combination of OH, KAGAWA, and CHUNG teaches the semiconductor package of claim 15.
OH further discloses wherein the first dummy pad 344D of the first second semiconductor chip of the plurality of second semiconductor chips 200 is in contact with the second bonding insulating film 236/302D of the second second semiconductor chip of the plurality of second semiconductor chips 200 (first dummy pad 344D is in contact with second dummy pad 342D which is further in contact with second bonding insulating film 236/302D, therefore first dummy pad 344D is in contact with second bonding insulating film 236/302D, Fig. 13B).
Claim 19, The combination of OH, KAGAWA, and CHUNG teaches the semiconductor package of claim 15.
OH further discloses wherein the second maximum width W2 of the first dummy pad 344D is greater than a fourth maximum width of the through-via 314D (the second maximum width W2 of the first dummy pad 344D is greater than the fourth horizontal width W4, hereinafter fourth maximum width W4, of the through-via 314D, [0050], Fig. 13B).
Claim 20, The combination of OH, KAGAWA, and CHUNG teaches the semiconductor package of claim 15.
OH further discloses wherein each of the plurality of second semiconductor chips 200 further includes a second dummy pad disposed in the second bonding insulating film 236/302D and insulated from the through-via 314D (front thermal pad portion 342D, hereinafter second dummy pad 342D, is insulated from the through-via 314D and disposed in the second bonding insulating film 236/302D, Fig. 13B), and
wherein the second dummy pad 342D is in contact with the first dummy pad 344D (second dummy pad 342D is in contact with the first dummy pad 344D, Fig. 13B).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over OH in view of KAGAWA further in view of CHUNG and further in view of Hu (US 20190164919 A1).
Claim 16, The combination of OH, KAGAWA, and CHUNG teaches the semiconductor package of claim 15.
The combination of OH, KAGAWA, and CHUNG does not explicitly teach wherein the second maximum width is in a range of about 0.5 times to about 0.8 times of the first maximum width.
However, Hu discloses wherein a second maximum width (width W1, Fig. 2) of a pad is in a range of about 0.5 times to about 0.8 times of a first maximum width (width W3, Fig. 2) of a pad (width W1 can be between 0.5μm and 4.0μm, [0032]; width W3 can be between 1.0μm and 4.5μm, [0036]; the ratio of W1 to W3 can be 0.5μm / 1.0μm = 0.5; the ratio of W1 to W3 can be 3.2μm / 4.0μm = 0.8).
The second maximum width and first maximum width are result effective variables as one would have chosen them to be shaped so that dishing would be prevented during CMP (KAGAWA, [0092]) and so that part of the bonding surface could be more firmly protected (KAGAWA, [0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by the combination of OH, KAGAWA, and CHUNG with the teaching disclosed by KAGAWA and ranges disclosed by Hu as it would merely result in an optimization of result effective variables.
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Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over OH in view of KAGAWA further in view of CHUNG further in view of Hu and further in view of Yu (US 20150200185 A1).
Claim 17, The combination of OH, KAGAWA, CHUNG and Hu teaches the semiconductor package of claim 16.
The combination of OH, KAGAWA, CHUNG, and Hu does not explicitly teach wherein the first dummy pad has a third maximum width in a second direction, and
wherein the third maximum width is about 1.6 times of the second maximum width.
However, Yu discloses wherein a first metal pad has a third maximum width in a second direction, and
wherein the third maximum width is about 1.6 times of the second maximum width (L1/W1 may be greater than about 1.2, or greater than about 1.6, [0023], Fig. 9A).
The second maximum width and third maximum width are result effective variables as one would have chosen them to be shaped so that dishing would be prevented during CMP (KAGAWA, [0092]) and so that part of the bonding surface could be more firmly protected (KAGAWA, [0093]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention disclosed by the combination of OH, KAGAWA, CHUNG, and Hu with the teaching disclosed by KAGAWA and ranges disclosed by Yu as it would merely result in an optimization of result effective variables.
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Yu Fig. 9
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
SAWADA (US 20220189905 A1) discloses a first pad disposed in a first insulating film being in contact with a second bonding insulating film in Fig. 5.
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/MICHAEL M VANYO/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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