CTNF 18/818,154 CTNF 83016 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-27 AIA Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 15/869,582 , filed on January 12, 2018 . Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on August 28, 2024 was filed on the filing date of the application on August 28, 2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings 06-37 AIA The drawings were received on August 28, 2024 . These drawings are accepted . Double Patenting 08-33 AIA The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-36 AIA Claim s 1-20 are rejected on the ground of non-statutory double patenting as being unpatentable over claim s 1-20 of U.S. Patent No. 11,501,139 in view of Sun et al. (US 10,424,069). Please see the tables below . Present Application #18/818,154 1 2 3 4 5 6 7 8 9 10 U.S. Patent #11,501,139 1 2 3 4 5 6 7 8 9 10 Present Application #18/818,154 11 12 13 14 15 16 17 18 19 20 U.S. Patent #11,501,139 11 12 13 14 15 16 17 18 19 20 Present Application #18/818,154 Claim 1 U.S. Patent #11,501,139 Claim 1 A graphics processor comprising: A machine-learning accelerator comprising: an interconnect to a fabric interface; and a graphics processing cluster including a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data crossbar, at least one multiprocessor including a compute circuitry configured to: a multiprocessor to execute parallel threads of an instruction stream, the multiprocessor including a compute unit, the compute unit including a set of functional units, each functional unit to execute at least one of the parallel threads of the instruction stream; and wherein the compute unit includes compute logic configured to execute at least one single instruction to scale an input tensor associated with a layer of a neural network according to a scale factor, execute a single instruction to scale an input tensor associated with a layer of a neural network according to a scale factor, the input tensor stored in a floating-point data type, the input tensor stored in a floating-point data type, the input tensor scaled to enable a data distribution of data of the input tensor to be represented by a 16-bit floating point data type. the compute logic to scale the input tensor to enable a data distribution of data of the input tensor to be represented by a 16-bit floating point data type. Claim 1 of the present application differs from claim 1 of the patent application in that claim 1 of the present application recites its graphics processor comprising “…an interconnect to a fabric interface; and a graphics processing cluster including a plurality of multiprocessors interconnected via a data crossbar…” where claim 1 of the patent application does not recite such limitation. However, claim 1 of the patent application further recites, “…a multiprocessor to execute parallel threads of an instruction stream, the multiprocessor including a compute unit, the compute unit including a set of functional units, each functional unit to execute at least one of the parallel threads of the instruction stream…” Sun et al. disclose a graphics processor ( Figure 3, parallel processing unit (PPU) 300, where column 11, lines 4-9 notes PPU may be a graphics processing unit (GPU) ) comprising: an interconnect to a fabric interface ( hub 330 to NVLink interconnect 310 ); and a graphics processing cluster ( one or more general processing clusters (GPCs) 350 ) including a plurality of multiprocessors ( streaming multi-processors (SMs) 440, where Figure 4A, column 14, lines 30-32 notes SMs 440 comprised within data processing clusters (DPCs) 420 of GPCs 350, and lines 40-42 notes each SM 440 comprises a programmable streaming processor configured to process tasks represented by a number of threads ), the plurality of multiprocessors interconnected via a data crossbar ( crossbar (Xbar) 370, where column 12, lines 63-67 notes Xbar 370 is an interconnect network that couples many of the units of the PPU 300 to other units of the PPU 300, e.g. SMs interconnected to other SMs ). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify claim 1 of the patent application with such structure to efficiently execute the threads in parallel to perform the method as described ( see column 14, lines 40-67 of Sun et al. ). Present Application #18/818,154 Claim 2 U.S. Patent #11,501,139 Claim 2 The graphics processor as in claim 1, The machine-learning accelerator as in claim 1, the compute circuitry to compute an exponent bias based on an absolute maximum value of the input tensor and a dynamic range of the 16-bit floating point data type. the compute logic to compute an exponent bias based on an absolute maximum value of the input tensor and a dynamic range of the 16-bit floating point data type. Present Application #18/818,154 Claim 3 U.S. Patent #11,501,139 Claim 3 The graphics processor as in claim 2, The machine-learning accelerator as in claim 2, the compute circuitry to convert weights and activations of the layer of the neural network to scaled 16-bit floating-point tensors. the compute logic to convert weights and activations of the layer of the neural network to scaled 16-bit floating-point tensors. Present Application #18/818,154 Claim 4 U.S. Patent #11,501,139 Claim 4 The graphics processor as in claim 3, The machine-learning accelerator as in claim 3, the compute circuitry to perform a compute operation on the scaled 16-bit floating-point tensors, the compute operation including one a multiply, add, or a fused multiply-add. the compute logic to perform a compute operation on the scaled 16-bit floating-point tensors, the compute operation including one a multiply, add, or a fused multiply-add. Present Application #18/818,154 Claim 5 U.S. Patent #11,501,139 Claim 5 The graphics processor as in claim 4, The machine-learning accelerator as in claim 4, the compute circuitry to generate a set of 32-bit intermediate results in response to the compute operation on the scaled 16-bit floating-point tensors. the compute logic to generate a set of 32-bit intermediate results in response to the compute operation on the scaled 16-bit floating-point tensors. Present Application #18/818,154 Claim 6 U.S. Patent #11,501,139 Claim 6 The graphics processor as in claim 5, The machine-learning accelerator as in claim 5, the compute circuitry to re-scale the set of 32-bit intermediate results using the exponent bias and down-convert the set of 32-bit intermediate results into scaled 16-bit floating point values. the compute logic to re-scale the set of 32-bit intermediate results using the exponent bias and down-convert the set of 32-bit intermediate results into scaled 16-bit floating point values. Present Application #18/818,154 Claim 7 U.S. Patent #11,501,139 Claim 7 The graphics processor as in claim 1, The machine-learning accelerator as in claim 1, the compute circuitry to perform a compute operation on scaled 16-bit floating-point tensors to generate intermediate values, the compute logic to perform a compute operation on scaled 16-bit floating-point tensors to generate intermediate values, determine if the intermediate values are close to saturation, and determine if the intermediate values are close to saturation, and re-scale the intermediate values when the intermediate values are close to saturation. re-scale the intermediate values when the intermediate values are close to saturation. Present Application #18/818,154 Claim 8 U.S. Patent #11,501,139 Claim 8 The graphics processor as in claim 7, The machine-learning accelerator as in claim 7, the compute circuitry to update an exponent bias value after re-scale of the intermediate values. the compute logic to update an exponent bias value after the re-scale of the intermediate values. Present Application #18/818,154 Claim 9 U.S. Patent #11,501,139 Claim 9 A method implemented via a machine-learning accelerator, the method comprising: A method implemented via a machine-learning accelerator, the method comprising: executing at least one single instruction to perform a scaled tensor compute operation; executing parallel threads of a parallel instruction stream, the parallel instruction stream including at least one single instruction to perform a scaled tensor compute operation; in response to the at least one single instruction, scaling data of an input tensor associated with a layer of a neural network according to a scale factor, in response to the single instruction, scaling data of an input tensor associated with a layer of a neural network according to a scale factor, executing a compute operation on scaled data of the input tensor, and executing one or more compute operations on scaled data of the input tensor, and re-scaling computed data of the compute operation to generate re-scaled computed data; re-scaling computed data of the compute operations to generate re-scaled computed data; down-converting the re-scaled computed data; and down-converting the re-scaled computed data; and storing down-converted re-scaled computed data to a 16-bit floating-point data type. storing down-converted re-scaled computed data to a 16-bit floating-point data type. Claim 9 of the present application differs from claim 9 of the patent application in that claim 9 of the present application is broader in scope than claim 9 of the patent application, thus encompasses that of the patent application. Present Application #18/818,154 Claim 10 U.S. Patent #11,501,139 Claim 10 The method as in claim 9, additionally comprising The method as in claim 9, additionally comprising computing an exponent bias based on an absolute maximum value of the input tensor and a dynamic range of the 16-bit floating-point data type and scaling the data of the input tensor using the exponent bias. computing an exponent bias based on an absolute maximum value of the input tensor and a dynamic range of the 16-bit floating-point data type and scaling the data of the input tensor using the exponent bias. Present Application #18/818,154 Claim 11 U.S. Patent #11,501,139 Claim 11 The method as in claim 10, additionally comprising The method as in claim 10, additionally comprising converting weights and activations of the layer of the neural network to scaled 16-bit floating-point tensors. converting weights and activations of the layer of the neural network to scaled 16-bit floating-point tensors. Present Application #18/818,154 Claim 12 U.S. Patent #11,501,139 Claim 12 The method as in claim 11, wherein The method as in claim 11, wherein executing the compute operation on the scaled data of the input tensor includes executing a multiply, add, or a fused multiply-add operation. executing the one or more compute operations on the scaled data of the input tensor includes executing a multiply, add, or a fused multiply-add operation. Present Application #18/818,154 Claim 13 U.S. Patent #11,501,139 Claim 13 The method as in claim 12, wherein The method as in claim 12, wherein computed data of the compute operation include a set of 32-bit intermediate results. computed data of the compute operations include a set of 32-bit intermediate results. Present Application #18/818,154 Claim 14 U.S. Patent #11,501,139 Claim 14 The method as in claim 13, additionally comprising The method as in claim 13, additionally comprising re-scaling the set of 32-bit intermediate results using the exponent bias and down-converting the set of 32-bit intermediate results into scaled 16-bit floating-point values. re-scaling the set of 32-bit intermediate results using the exponent bias and down-converting the set of 32-bit intermediate results into scaled 16-bit floating-point values. Present Application #18/818,154 Claim 15 U.S. Patent #11,501,139 Claim 15 The method as in claim 9, additionally comprising: The method as in claim 9, additionally comprising: performing a compute operation on scaled 16-bit floating-point tensors to generate intermediate values; performing a compute operation on scaled 16-bit floating-point tensors to generate intermediate values; determining if the intermediate values are close to saturation; determining if the intermediate values are close to saturation; re-scaling the intermediate values in response to determining that the intermediate values are close to saturation; and re-scaling the intermediate values in response to determining that the intermediate values are close to saturation; and updating an exponent bias value after re-scaling the intermediate values. updating an exponent bias value after re-scaling the intermediate values. Present Application #18/818,154 Claim 16 U.S. Patent #11,501,139 Claim 16 A graphics processing system comprising: A data processing system comprising: a memory device; and a memory device; and a graphics processor a general-purpose graphics processing unit including an instruction decoder to decode a single instruction including multiple operands into a single decoded instruction, comprising a graphics processing cluster including a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data crossbar, at least one multiprocessor including a compute circuitry configured to: execute at least one single instruction to scale an input tensor associated with a layer of a neural network according to a scale factor, the input tensor stored in a floating-point data type, the input tensor scaled to enable a data distribution of data of the input tensor to be represented by a 16-bit floating point data type. at least one of the multiple operands associated with input tensor data of a layer of a neural network, and a compute unit including compute logic configured to execute the single instruction to scale data of the input tensor to enable a data distribution of data of the input tensor to be represented by a 16-bit floating point data type. Claim 16 of the present application differs from claim 16 of the patent application in that claim 16 of the present application recites its graphics processor, “…comprising a graphics processing cluster including a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data crossbar, at least one multiprocessor including a compute circuitry…” where claim 1 of the patent application does not recite such limitation. However, Sun et al. disclose a graphics processor ( Figure 3, parallel processing unit (PPU) 300, where column 11, lines 4-9 notes PPU may be a graphics processing unit (GPU) ) comprising a graphics processing cluster ( one or more general processing clusters (GPCs) 350 ) including a plurality of multiprocessors ( streaming multi-processors (SMs) 440, where Figure 4A, column 14, lines 30-32 notes SMs 440 comprised within data processing clusters (DPCs) 420 of GPCs 350, and lines 40-42 notes each SM 440 comprises a programmable streaming processor configured to process tasks represented by a number of threads ), the plurality of multiprocessors interconnected via a data crossbar ( crossbar (Xbar) 370, where column 12, lines 63-67 notes Xbar 370 is an interconnect network that couples many of the units of the PPU 300 to other units of the PPU 300, e.g. SMs interconnected to other SMs ), at least one multiprocessor including a compute circuitry ( Figure 5A, column 16, lines 33-39 notes each SM 440 includes an instruction cache 505, one or more scheduler units 510, a register file 520, one or more processing cores 550, one or more special function units (SFUs) 552, one or more load/store units (LSUs) 554, an interconnect network 580, and a shared memory/L1 cache 570 )…” Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify claim 1 of the patent application with such structure to efficiently execute threads in parallel to perform the method as described ( see column 14, lines 40-67 of Sun et al. ). Present Application #18/818,154 Claim 17 U.S. Patent #11,501,139 Claim 17 The graphics processing system as in claim 16, the compute circuitry to: The data processing system as in claim 16, the compute logic to: compute an exponent bias based on an absolute maximum value of the input tensor and a dynamic range of the 16-bit floating point data type; compute an exponent bias based on an absolute maximum value of the input tensor and a dynamic range of the 16-bit floating point data type; convert weights and activations of the layer of the neural network to scaled 16-bit floating-point tensors; convert weights and activations of the layer of the neural network to scaled 16-bit floating-point tensors; perform a compute operation on the scaled 16-bit floating-point tensors; perform a compute operation on the scaled 16-bit floating-point tensors; generate a set of 32-bit intermediate results in response to the compute operation on the scaled 16-bit floating-point tensors; generate a set of 32-bit intermediate results in response to the compute operation on the scaled 16-bit floating-point tensors; re-scale the set of 32-bit intermediate results using the exponent bias; and re-scale the set of 32-bit intermediate results using the exponent bias; and down-convert the set of 32-bit intermediate results into scaled 16-bit floating point values. down-convert the set of 32-bit intermediate results into scaled 16-bit floating point values. Present Application #18/818,154 Claim 18 U.S. Patent #11,501,139 Claim 18 The graphics processing system as in claim 17, The data processing system as in claim 17, the compute operation including one a multiply, add, or a fused multiply-add. the compute operation including one a multiply, add, or a fused multiply-add. Present Application #18/818,154 Claim 19 U.S. Patent #11,501,139 Claim 19 The graphics processing system as in claim 16, The data processing system as in claim 16, the compute circuitry to perform a compute operation on scaled 16-bit floating-point tensors to generate intermediate values, the compute logic to perform a compute operation on scaled 16-bit floating-point tensors to generate intermediate values, determine if the intermediate values are close to saturation, and determine if the intermediate values are close to saturation, and re-scale the intermediate values when the intermediate values are close to saturation. re-scale the intermediate values when the intermediate values are close to saturation. Present Application #18/818,154 Claim 20 U.S. Patent #11,501,139 Claim 20 The graphics processing system as in claim 19, The data processing system as in claim 19, the compute circuitry to update an exponent bias value after re-scale of the intermediate values. the compute logic to update an exponent bias value after the re-scale of the intermediate values . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-6 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun et al. (US 10,424,069) in view of Ginsburg et al. (US 12,299,577) . As to claim 1, Sun et al. disclose a graphics processor ( Figure 3, parallel processing unit (PPU) 300, where column 11, lines 4-9 notes PPU may be a graphics processing unit (GPU) ) comprising: an interconnect to a fabric interface ( hub 330 to NVLink interconnect 310 ); and a graphics processing cluster ( one or more general processing clusters (GPCs) 350 ) including a plurality of multiprocessors ( streaming multi-processors (SMs) 440, where Figure 4A, column 14, lines 30-32 notes SMs 440 comprised within data processing clusters (DPCs) 420 of GPCs 350, and lines 40-42 notes each SM 440 comprises a programmable streaming processor configured to process tasks represented by a number of threads ), the plurality of multiprocessors interconnected via a data crossbar ( crossbar (Xbar) 370, where column 12, lines 63-67 notes Xbar 370 is an interconnect network that couples many of the units of the PPU 300 to other units of the PPU 300, e.g. SMs interconnected to other SMs ), at least one multiprocessor including a compute circuitry ( Figure 5A, column 16, lines 33-39 notes each SM 440 includes an instruction cache 505, one or more scheduler units 510, a register file 520, one or more processing cores 550, one or more special function units (SFUs) 552, one or more load/store units (LSUs) 554, an interconnect network 580, and a shared memory/L1 cache 570 ) configured to: execute at least one single instruction ( column 14, lines 40-55 notes each SM 440 is multi-threaded and configured to execute a plurality of threads (e.g. 32 threads) from a particular group of threads concurrently, where SMs 440 may implement a SIMD (Single-Instruction, Multiple-Data) architecture where each thread in a group of threads (e.g. a warp) is configured to process a different set of data based on the same set of instructions, where all threads in the group of threads execute the same instructions or SMs 440 may implement a SIMT (Single-Instruction, Multiple Thread) architecture where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but where individual threads in the group of threads are allowed to diverge during execution ) to scale an input tensor ( Figure 5A, column 17, lines 32 thru column 18, lines 3 notes SMs includes L processing cores 550, which may further include 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores, where tensor cores perform matrix operations, e.g. operate on 16-bit floating point input data with 32-bit floating point accumulation, the 16-bit floating point multiply requires 64 operations and results in a full precision product that is then accumulated using 32-bit floating point addition with the other intermediate products for a 4×4×4 matrix multiply, where operating on 16-bit floating point input data, e.g. tensor, with 32-bit floating point accumulation, considered scaling ). Sun et al. differ from the invention defined in claim 1 in that Sun et al. do not disclose its streaming multiprocessors “… to scale an input tensor associated with a layer of a neural network according to a scale factor, the input tensor stored in a floating-point data type, the input tensor scaled to enable a data distribution of data of the input tensor to be represented by a 16-bit floating point data type…” Ginsburg et al. disclose a graphics processor ( Figure 4, graphics subsystem 405 )…configured to ( Figure 3 )…scale an input tensor ( e.g. a matrix ) associated with a layer of a neural network ( e.g. layer of a neural network ) according to a scale factor ( e.g. scale factor ), the input tensor stored in a floating-point data type ( float16 format ), the input tensor scaled to enable a data distribution of data of the input tensor to be represented by a 16-bit floating point data type ( column 4, lines 63 thru column 5, lines 38 notes improving neural network algorithms using a modified float16 format in which a matrix X of data values is represented as a tuple (a,v[.]), where a is a float scale factor and v[.] contains the values of X rescaled by a, such that the value of any element X[i] is equal to a*v[i], where the modification of the float16 data format offers increased protection from overflow and underflow relative to the standard float16 format by extending the potential dynamic range of values, thus any matrix X can be converted to the modified float16 format without significant precision loss whenever the current range of X fits into the modified float16 range of 2 29 ~10 9 ). It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Sun et al.’s system and method of operating on tensors with Ginsburg et al.’s method of scaling tensors according to a scale factor to improve neural network training algorithms to efficiently avoid overflow and underflow during matrix-matrix multiplication ( see column 4, lines 63 thru column 5, lines 35 and column 6, lines 1-7 of Ginsburg et al. ). As to claim 2, Sun et al. modified with Ginsburg et al. disclose the compute circuitry to compute an exponent bias based on an absolute maximum value of the input tensor and a dynamic range of the 16-bit floating point data type ( modified with Ginsburg, column 5, lines 5-23 notes converting single-precision float into a half-precision float16 format that uses scalars for exponent extension, by using a common scalar value for all elements in a tensor array, the limits of the numerical range of the matrix can be extended between the range of [2 229 ~10- 9 , 2 29 ~10 9 ], to estimate the range of a matrix X, the average of the absolute values of non-zero elements in X (as mean(X)), and the maximal absolute value (amax(X)), and using these values, the range of matrix (X) can be estimated to approximate max(x)/mean (X) ). As to claim 3, Sun et al. modified with Ginsburg et al. disclose the compute circuitry to convert weights and activations of the layer of the neural network to scaled 16-bit floating-point tensors ( modified with Ginsburg, column 5, lines 46-67 notes step 105, the data at each neuron is manipulated according to pre-determined parameters (weights), and a resulting weighted output is generated and passed at step 107 to the next neuron in the next layer in sequence, the neuron in each layer receives the weighted output from the previous neuron as input, and the process is propagated forward at step 109 for each intervening layer between the input and output layers, where column 6, lines 1-60 further notes appropriate scalar values need to be calculated to effectively avoid overflow and underflow during matrix-matrix multiplication using the modified float16 format, where column 8, lines 52-55 notes to avoid the issue of vanishing or exploding activations (due to underflow and overflow, respectively) the rescaling operations as described are performed ). As to claim 4, Sun et al. modified with Ginsburg et al. disclose the compute circuitry to perform a compute operation on the scaled 16-bit floating-point tensors, the compute operation including one a multiply, add, or a fused multiply-add ( modified with Ginsburg, column 5, lines 39 thru column 6, lines 60, e.g. matrix-matrix multiplication, column 6, lines 61 thru column 7, lines 37, e.g. matrix-matrix convolution, and column 7, lines 38-47, e.g. tensor operations, e.g. tensor-scalar multiplication, e.g. used to convert data between scaled and un-scaled values, and tensor-tensor addition under the modified float16 format ). As to claim 5, Sun et al. modified with Ginsburg et al. disclose the compute circuitry to generate a set of 32-bit intermediate results in response to the compute operation on the scaled 16-bit floating-point tensors ( modified with Ginsburg, column 5, lines 23-35 notes conversion from the single-precision float32 format to the modified float16 format and the inverse transformation from the modified float16 format to single-precision float ). As to claim 6, Sun et al. modified with Ginsburg et al. disclose the compute circuitry to re-scale the set of 32-bit intermediate results using the exponent bias and down-convert the set of 32-bit intermediate results into scaled 16-bit floating point values ( modified with Ginsburg, column 5, lines 6-35 notes converting single-precision float into a half-precision float16 format that uses scalars for exponent extension, where conversion may be from the single-precision float32 format to the modified float16 format ). As to claim 16, Sun et al. modified with Ginsburg et al. disclose a graphics processing system ( Sun, Figure 5B, system 565 ) comprising: a memory device ( Sun, main memory 540 ); and a graphics processor ( Sun, e.g. one or more PPUs 300, further illustrated in Figure 3, where column 11, lines 4-9 notes PPU may be a graphics processing unit (GPU) ) comprising a graphics processing cluster ( Sun, one or more general processing clusters (GPCs) 350 ) including a plurality of multiprocessors ( Sun, streaming multi-processors (SMs) 440, where Figure 4A, column 14, lines 30-32 notes SMs 440 comprised within data processing clusters (DPCs) 420 of GPCs 350, and lines 40-42 notes each SM 440 comprises a programmable streaming processor configured to process tasks represented by a number of threads ), the plurality of multiprocessors interconnected via a data crossbar ( Sun, crossbar (Xbar) 370, where column 12, lines 63-67 notes Xbar 370 is an interconnect network that couples many of the units of the PPU 300 to other units of the PPU 300, e.g. SMs interconnected to other SMs ), at least one multiprocessor including a compute circuitry ( Sun, Figure 5A, column 16, lines 33-39 notes each SM 440 includes an instruction cache 505, one or more scheduler units 510, a register file 520, one or more processing cores 550, one or more special function units (SFUs) 552, one or more load/store units (LSUs) 554, an interconnect network 580, and a shared memory/L1 cache 570 ) configured to perform the method as performed by the multiprocessor of the graphics processor of claim 1 ( Sun, modified with Ginsburg ). Please see the rejection and rationale of claim 1. Claim 17 is similar in scope to claims 2-6 combined, and are therefore rejected under similar rationale. Claim 18 is similar in scope to claim 4, and is therefore rejected under similar rationale . Allowable Subject Matter Claims 9-15 would be allowable if the Double Patenting rejection may be overcome. Claims 7, 8, 19, and 20 would be allowable if the Double Patenting rejection may be overcome AND if rewritten in independent form including ALL of the limitations of the base claim AND any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding independent claim 9, the prior art of record discloses similar limitations of the claimed invention as outlined in independent claims 1 and 16 above. However, the prior art of record fails to teach or suggest, singly or combined, the limitations of independent claim 9 as recited as a whole. Dependent claims 10-15 are indicated allowable for depending upon indicated allowable claim 9. Regarding dependent claims 7 and 19, the prior art of record fails to teach or suggest, singly or combined, the limitations of the claims as recited. Dependent claims 8 and 20 are indicated allowable for depending upon indicated allowable claims 7 and 19, respectively . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACINTA M CRAWFORD whose telephone number is (571)270-1539. The examiner can normally be reached 8:30a.m. to 4:30p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, King Y. Poon can be reached at (571)272-7440. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACINTA M CRAWFORD/Primary Examiner, Art Unit 2617 Application/Control Number: 18/818,154 Page 2 Art Unit: 2617 Application/Control Number: 18/818,154 Page 3 Art Unit: 2617 Application/Control Number: 18/818,154 Page 4 Art Unit: 2617 Application/Control Number: 18/818,154 Page 5 Art Unit: 2617 Application/Control Number: 18/818,154 Page 6 Art Unit: 2617 Application/Control Number: 18/818,154 Page 7 Art Unit: 2617 Application/Control Number: 18/818,154 Page 8 Art Unit: 2617 Application/Control Number: 18/818,154 Page 9 Art Unit: 2617 Application/Control Number: 18/818,154 Page 10 Art Unit: 2617 Application/Control Number: 18/818,154 Page 11 Art Unit: 2617 Application/Control Number: 18/818,154 Page 12 Art Unit: 2617 Application/Control Number: 18/818,154 Page 13 Art Unit: 2617 Application/Control Number: 18/818,154 Page 14 Art Unit: 2617 Application/Control Number: 18/818,154 Page 16 Art Unit: 2617
Prosecution Insights