The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of the embodiment of figure 2 in the reply filed on 09/28/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Quizan et al. (2025/0006630) in view of Wakefield (5,362,679).Regarding claim 1, Quizan et al. teach in figures 1-9 and related text a semiconductor package comprising:
a plurality of semiconductor chips 110, 120 (see figure 1A);
a plurality of bonding pads 1363 (see figure 8) between two of the plurality of semiconductor chips;
a bonding insulating layer 1634, 1626 (see also paragraph [0023]) surrounding the plurality of bonding pads between the two of the plurality of semiconductor chips; and
a void controller 370a (see figure 3C) between the plurality of bonding pads,
wherein the plurality of bonding pads 110, 120 are directly connected (see figure 1A) to the two of the plurality of semiconductor chips,
wherein the bonding insulating layer (see figures 8-9) is directly connected to the two of the plurality of semiconductor chips,
wherein the void controller is a cavity defined by the bonding insulating layer, one of the plurality of semiconductor chips, and the bonding insulating layer, or the one of the plurality of semiconductor chips and the bonding insulating layer.
Quizan et al. do not teach that the void controller is filled with a gas.
Wakefield teaches in related text that the void controller is filled with a gas.
Wakefield further teaches in figure 1 and related text a void controller 20 is filled with a gas.
Quizan et al. and Wakefield are analogous art because they are directed to packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Quizan because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to fill the void controller with a gas, as taught by Wakefield, in Quizan et al.’s device, in order to improve the device characteristics by hermetic sealing the cavity.
The combination is motivated by the teachings of Wakefield who points out the advantages of filling the void controller with a gas (see e.g. column 2, lines 1-10).
Regarding claim 2, Quizan et al. do not teach that a vertical length of the void controller is equal to or less than a vertical length of the bonding insulating layer.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a vertical length of the void controller equal to or less than a vertical length of the bonding insulating layer, in prior art’s device in order to optimize and adjust the device characteristics according to the requirements of the application in hand.
Regarding claim 3, in the combined device, the void controller is spaced apart from the plurality of bonding pads with a portion of the bonding insulating layer therebetween.
Regarding claim 4, Quizan et al. teach in figures 1-9 and related text that the void controller is defined by the one of the plurality of semiconductor chips and the bonding insulating layer.
Regarding claim 5, Quizan et al. teach in figures 1-9 and related text that the void controller is spaced apart from a first semiconductor chip among the two of the plurality of semiconductor chips with a first portion of the bonding insulating layer therebetween, and the void controller is spaced out from a second semiconductor chip among the two of the plurality of semiconductor chips with a second portion of the bonding insulating layer therebetween.
Regarding claim 6, Quizan et al. teach in figure 3C and related text that the void controller 370A has a line shape extending in one direction.
Regarding claim 7, Quizan et al. do not teach that the void controller has a cross shape. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the void controller in a cross shape, in prior art’s device in order to optimize and adjust the device characteristics according to the requirements of the application in hand.
Regarding claim 8, Quizan et al. teach in figure 8 and related text that the plurality of bonding pads are provided in at least one row, at least one column, or combinations thereof, but does not explicitly state that the void controller overlaps with the at least one row of the plurality of bonding pads in a first horizontal direction or overlaps with the at least one column of the plurality of bonding pads in a second horizontal direction that crosses the first horizontal direction.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the void controller overlaps with the at least one row of the plurality of bonding pads in a first horizontal direction or overlaps with the at least one column of the plurality of bonding pads in a second horizontal direction that crosses the first horizontal direction, in prior art’s device in order to form one functional device as intended by Quizan et al.
Regarding claim 9, Quizan et al. teach in figure 3C and related text that one end of the void controller faces a chip edge of the plurality of semiconductor chips.
Regarding claims 10 and 17, in the combined device, Quizan et al. teach in figure 3C and related text that the void controller has a slit shape, a groove shape, or a recess shape.
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (12,046,573) in view of Quizan et al. (2025/0006630) and Wakefield (5,362,679).
Regarding claims 18 and 11, Kim et al. teach in figures 2A, 2B and related text a semiconductor package comprising:
a first semiconductor chip 41 comprising:
a first semiconductor substrate 60 comprising an active surface and an inactive surface opposite to each other; and
first through-electrodes 62 passing through the first semiconductor substrate; and
second semiconductor chips 43a, 43b, each comprising:
a second semiconductor substrate 60 comprising an active surface and an inactive surface opposite to each other; and
second through-electrodes 62 passing through the second semiconductor substrate, wherein the second semiconductor chips are stacked on the first semiconductor chip so that the active surface of the second semiconductor substrate faces towards the inactive surface of the first semiconductor substrate,
wherein the semiconductor package further comprises:
first bonding pads 71, 75 (see figures 3A and 4A) between the first semiconductor chip and a lowermost second semiconductor chip among the second semiconductor chips, the first bonding pads electrically connecting the first through-electrodes and the second through-electrodes of the lowermost second semiconductor chip;
second bonding pads (another 71, 75) between a pair of the second semiconductor chips, among the second semiconductor chips, that are adjacent to each other, the second bonding pads electrically connecting the second through-electrodes of one second semiconductor chip among the pair of the second semiconductor chips to another second semiconductor chip among the pair of the second semiconductor chips;
a first bonding insulating layer 67 surrounding the first bonding pads, and between the first semiconductor chip and the lowermost second semiconductor chip;
a second bonding insulating layer (another 67) surrounding the second bonding pads, and between the pair of the second semiconductor chips; and
a first void controller H (see figure 5B) that is between and separated from the first bonding pads, and wherein the first void controller comprises a cavity H that is defined by at least one from among the first bonding insulating layer, the first semiconductor chip, and the lowermost second semiconductor chip.
Kim et al. do not teach that pads 71, 75 are bonding pads.
Kim et al. teach in figure 7F and related text using pads 15 as bonding pads.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use pads 71, 75 are bonding pads in Kim et al.’s device in order to improve the structural integrity of the device.
Kim et al. also do not explicitly state a first void controller that is between and separated from the first bonding pads, and wherein the first void controller comprises a cavity that is defined by at least one from among the first bonding insulating layer, the first semiconductor chip, and the lowermost second semiconductor chip.
Quizan et al. teach in figures 1-9 and related text a first void controller 370A that is between and separated from the first bonding pads, and wherein the first void controller comprises a cavity that is defined by at least one from among the first bonding insulating layer, the first semiconductor chip, and the lowermost second semiconductor chip.
Wakefield teaches in figure 1 and related text a first void controller 20 that is between and separated from the first bonding pads (un-numbered), and wherein the first void controller comprises a cavity that is defined by at least one from among the first bonding insulating layer, the first semiconductor chip, and the lowermost second semiconductor chip.
Wakefield further teaches in column 2, lines 1-10 the advantages of filling the void controller with a gas.
Quizan et al., Kim et al. and Wakefield are analogous art because they are directed to packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a first void controller that is between and separated from the first bonding pads, and wherein the first void controller comprises a cavity that is defined by at least one from among the first bonding insulating layer, the first semiconductor chip, and the lowermost second semiconductor chip, as taught by Quizan et al. and Wakefield, in Kim et al.’s device, in order to improve the device characteristics by hermetic sealing the cavity.
Regarding claims 19 and 16, in the combined device, Wakefield teaches in figure 1 and related text a dummy support substrate (the top part of molding 10) on an uppermost second semiconductor chip 12 among the second semiconductor chips; support bonding pads (un-numbered) between the uppermost second semiconductor chip and the dummy support substrate; a support bonding insulating layer 10 surrounding the support bonding pads and between the uppermost second semiconductor chip and the dummy support substrate; and a second void controller (the lower part of element 20) between and separated from the support bonding pads, wherein the second void controller comprises a cavity that is defined by at least one from among the support bonding insulating layer, the uppermost second semiconductor chip, and the dummy support substrate.
Regarding claim 20, in the combined device, Wakefield teaches in figure 1 and related text a package molding portion 10 on an upper surface of the first semiconductor chip 12 and on sidewalls of the second semiconductor chips.
Regarding claim 11, in the combined device, the first void controller comprises a cavity filled with a gas (as taught by Wakefield).
Regarding claim 12, in the combined device, the cavity of the first void controller is defined by the first bonding insulating layer and the first semiconductor chip, or by the second bonding insulating layer and one of the second semiconductor chips.
Regarding claim 13, in the combined device, the cavity of the first void controller is defined by the first bonding insulating layer, the first semiconductor chip, and the lowermost second semiconductor chip, or by the second bonding insulating layer and the pair of the second semiconductor chips.
Regarding claim 14, in the combined device, the first void controller is defined by the first bonding insulating layer or the second bonding insulating layer.
Regarding claim 15, in the combined device, the first void controller exposes a portion of an upper surface of the first semiconductor chip, exposes a portion of an upper surface of one of the second semiconductor chips, or exposes a portion of a lower surface of the one of the second semiconductor chips.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
10/11/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
