DETAILED ACTION
Claims 1,4,7-8,11,14-15,18 are amended. Claims 5,12,19 are canceled.
Claims 1-4, 6-11, 13-18, 20 are pending.
Priority: 8/28/2024
Assignee: Micron
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-4, 6-11, 13-18, 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
1.Amended Claims 1,8,15 are rejected for reciting a limitation with antecedent basis issues.
Amended Claim 1 recites, ‘storing… a first address translation metadata structure’. And further recites, ‘updating… a first address translation metadata structure’. Claims 8, 15 have the same issue.
2.Amended Claim 1 is rejected for reciting a limitation with antecedent basis issues.
Amended Claim 1 recites, ‘updating an address translation metadata pointer to reference….during address translation operations associated with the plurality of zoned namespaces….’ Here, ‘the plurality of zoned namespaces’ lacks antecedent basis.
Note: In the Remarks, the Applicant does not mention the relevant specification paragraph(s) that recite the amendment(s).
1.Amended Claims 1,8,15 are rejected for reciting a limitation that is unclear, inconsistent, and indefinite.
Amended Claim 1 recites, ‘switching to the second address translation metadata structure for subsequent address translation operations….’; ‘updating the address translation metadata pointer to point to the second address translation metadata structure during address translation operations….’.
The limitations are inconsistent with the spec because they recite two separate, unrelated steps, ‘switching to the second AT metadata structure…’ and then ‘updating the AT metadata pointer to point to the second AT metadata structure’.
Spec, Para-0040 discloses switching as a single-step by reciting, ‘To perform the switch, memory management component 113 can…. update an address translation metadata pointer by,….changing the address used by ….controller 115 to access primary metadata structure 152 to the address of the of secondary metadata structure 154’.
Based on the spec, original Claim 1 recites, ‘updating the address translation metadata pointer to point to the second address translation metadata structure….’. But amended Claim 1 conflicts with the spec and original Claim 1.
Since the spec does not support the two separate steps, amended claim 1 leads to uncertainty about the claim scope. The two-step limitations are ‘indefinite’ because it is unclear how the two steps relate to each other based on the spec. Hence claim 1 is rejected. Claims 8,15 have the same issue. Claims 2-4, 6-7,9-11,13-14,16-18,20 are rejected for failing to cure the deficiency from their respective parent claim by dependency. For examination, the spec is used.
2.Amended Claims 1,8,15 are rejected for reciting a limitation that is unclear, inconsistent, incorrect and indefinite.
Amended Claim 1 recites, ‘copying the first address translation metadata structure ….thus creating a second address translation metadata structure; switching to the second address translation metadata structure….’.
Amended Claim 1 recites that the first table/first AT metadata structure was merely stored on a first DRAM device, suggesting that the first table initially is empty because no updates have been made to it, i.e. no rows of the table have been added/modified/delated.
Claim 1 further recites copying the empty, first table in DRAM to create the second table on the second NVM device. This suggests that the second table is also an empty table. Accordingly, it is unclear why the switching (pointer update) to the second table is performed when both, the first and second tables are empty.
In Fig. 4, Para-0040, to allow switching, the spec recites the copy function after the first table has been updated via the update instruction. So the copied second table has updated data. The spec does not disclose copying empty tables. The spec does not disclose performing the switching operation with empty tables.
Though recited in claim 1, no ‘address translation operations’ are performed with empty tables.
Therefore, since no update has occurred in the first table, the limitation, ‘copying the first address translation metadata structure ….thus creating a second address translation metadata structure’, is unclear, hence indefinite. Therefore claim 1 is rejected. Claims 8,15 has the same issue. For examination, the spec is used.
As an aside, the spec does not disclose the specific details of the copy mechanism from DRAM to NVM. This suggests lack of possession, a potential 112(a).
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 1-4, 6-11, 13-18, 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Note: In the Remarks, the Applicant does not mention the relevant specification paragraph(s) that recite the amendment(s).
1.Amended Claims 1,8,15 are rejected for reciting limitations that are unsupported by the spec.
Amended Claim 1 recites, ‘storing, ….on a first memory device, a first address translation metadata structure’, during address translation operations associated with the plurality of zoned namespaces, a first address translation metadata structure’….’;‘copying ….’;‘switching….’;‘updating….’.
Amended Claim 1 recites updating an address translation metadata pointer to reference the first table during address translation operations….’. But the spec does not disclose updating the AT metadata pointer because the first table was stored on the first memory device.
As recited, the stored first table is empty. No update instruction has been received from the host or any other component, to update (row(s)) the first table. So the next limitation which recites updating the AT metadata pointer after merely storing the empty first table on the first memory device, being unsupported by the spec, shows lack of possession.
The limitation recites, ‘updating ….during address translation operations associated with the plurality of zoned namespaces’. But because of the cancellation, there is no update to the first table, and there are no ‘address translation operations’. The limitation is unsupported by the spec.
Due to the cancellation, amended claim 1 conflicts with claim 1 submitted as part of the original disclosure and the spec (e.g. Fig. 4).
Amended claim 1 recites updating the AT metadata pointer without any change occurring in the first table. This pointer update, without any table update, lacks written description support in the spec.
The spec does not disclose ‘switching’ the pointer from the first table to second table, when the tables have not been updated. Therefore, the two canceled limitations are essential limitations.
The cancellation of essential limitations and the improper broadening causes claim 1 to encompass subject matter not supported by the spec. Fig. 4 of the spec shows that the applicant did not possess the broadened scope recited in amended claim 1, at the time of the filing. Hence claim 1 recites new matter and is rejected. Amended claims 8,15 have the same issue. For examination, the spec is used.
Note: MPEP § 608.01(m) states that an independent claim is a standalone claim that must contain all the limitations necessary to define the invention.
Claim 8 has the same issue as claims 1,15. Since the first AT metadata structure has not been updated, receiving the update instruction is no-op.
2.Amended Claims 1,8,15 are rejected for reciting a limitation that is unsupported by the spec.
Amended Claim 1 recites, ‘updating an address translation metadata pointer….’, in limitation#2 and limitation#5.
But claim 1 does not recite how the address of the first table and the second table are determined.
Para-0032 of the spec recites, ‘the local memory 119 can include memory registers storing memory pointers, fetched data, etc’. This suggests that the metadata pointer is located in DRAM local memory 119.
Fig. 1 of the spec shows that the primary metadata structure 152/first table is located in DRAM local memory 119 of the controller and the secondary metadata structure 154/second table is in NVM device 140.
A pointer is a variable that stores an address. But how the metadata pointer located in DRAM local memory 119, is updated in the switching operation involving two different locations, DRAM vs NVM, lacks written description support.
The tables are in different locations (DRAM vs NVM). So they have different addresses. Amended Claim 1 does not recite how the address (address-1) of the first table is determined so that address-1 can be assigned to the metadata pointer (update-1). The claim does not recite how the address (address-2) of the second table is determined so after switching address-2 can be assigned to the metadata pointer (update-2). In essence, the claim recites a scope unsupported by the spec.
Accordingly, the limitations, ‘updating an address translation metadata pointer to reference….a first address translation metadata structure’, and, ‘updating the address translation metadata pointer to point to the second address translation metadata structure….’, recites a scope unsupported by the spec. Hence claim 1 is rejected. Claims 8,15 have the same issue.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-11, 13-18, 20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Harris et al (20200133849) in view of Bert (20210157720).
As per Claim 1, Harris discloses a method (Harris, [0023 - Fig. 3 shows method 300 to store namespace metadata]) comprising:
storing, by a processing device (Harris, [Fig. 1: processor 117]) of a memory sub-system controller (Harris, [0020 – In Fig. 1, controller 115 includes processor 117/processing device]), on a first memory device (Harris, [Fig. 1: local memory 119]; [0022 – Translation tables are stored in local memory 119]; [0017 - The local memory 119 can include memory registers storing memory pointers, fetched data, etc.; This is similar to Para-0032 of the spec]), a first address translation metadata structure (Harris, [0022 – In Fig. 2, namespace table 205 and L0 table 210 are stored in local DRAM memory 119, thereby representing the first AT metadata structure/first table]);
updating an address translation metadata pointer (Harris, [0017 - Local memory 119 can include memory registers storing memory pointers, fetched data, etc.; One of these pointers is used as an AT metadata pointer. The spec, Para-0032, also recites using a pointer from ‘memory pointers’. Since the spec does not define the pointer, it is interpreted as a global pointer]) to reference the first address translation metadata structure (Harris, [0024 – In Fig. 3, step 305, the processing device identifies a namespace identifier for a namespace associated with a first write instruction. The write instruction includes a namespace identifier. If the namespace identifier is ‘NS 0’, the controller finds ‘NS 0’ in namespace table 205]; [0035 - In Fig. 5C, in response to an add namespace request, the namespace manager creates a new entry in the namespace table with a pointer to the next available entry in the L0 table; So NS 0+L0 start is the address of the first table. This address is assigned to the AT metadata pointer thereby implying updating the AT metadata pointer to point to the first table]) during address translation operations associated with the plurality of zoned namespaces (Harris, [0020 - The memory subsystem 110 includes a namespace manager 113 that can divide storage on the storage system into namespaces]; [0022 – In Fig. 2, namespace table 205 includes an entry for each namespace that currently exists on the storage device, i.e. four namespaces: NS 0, NS 1, NS 2, NS 3; Since the claim does not define ‘zoned namespaces’, the citation is a valid interpretation]);
copying the first address translation metadata structure ([See 112(a)]) into a second memory device thus creating a second address translation metadata structure (Harris, [0027,0028 – In Fig. 3, step 320, the processing device generates a second write instruction that includes the data from the first write instruction, the logical address, and the physical address. At step 325, it sends the second write instruction to a memory device/second NVM device to store the data at the physical address, thereby creating the second address translation metadata structure/second table comprising namespace table 205 and L0 table 210 on the second memory device]; [Claim 1 - sending the second write instruction to a memory component/NVM, wherein the memory component stores the data at the physical address and also stores the logical address, including the namespace identifier, as metadata associated with the data; Since neither the claim nor the spec recite how the ‘copy’ is performed from DRAM to NVM, the citation is a valid interpretation]);
switching ([See 112(b)]) to the second address translation metadata structure for subsequent address translation operations associated with the plurality of zoned namespaces (Harris, [0028 - The second write instruction causes the logical address to be stored as metadata associated with the data in an area of the NVM memory device associated with the physical address, thereby implying switching to the second table; Here the update to the second table row(s) is made based on the updated row(s) in the first table]);
updating the address translation metadata pointer ([See 112(b)]) to point to the second address translation metadata structure during address translation operations (Harris, [0028 - The second write instruction causes the logical address to be stored as metadata associated with the data in an area of the memory component associated with the physical address; This implies that the L0 table of the second table is updated to store the logical address; The logical address is assigned to the global AT metadata pointer thereby updating the pointer to point to the second table]; [0026 – During a namespace update, the translation of the logical address includes entries in the hierarchical tables with consecutive portions of the logical address. The namespace identifier portion of the logical address identifies an entry in the namespace table 205, stored in namespace manager 113. When Fig. 2, L2 table 220 is reached, the contents of the entry is the physical address corresponding to the logical block address composed of the namespace identifier+namespace offset]) associated with the plurality of ([See 112(b)]) zoned namespaces (Harris, [0020 - The memory subsystem 110 includes a namespace manager 113 that can divide storage on the storage system into namespaces]; [0022 – In Fig. 2, namespace table 205 includes an entry for each namespace that currently exists on the storage device, i.e. four namespaces: NS 0, NS 1, NS 2, NS 3]).
With reference to the zoned namespace, Bert clarifies as follows,
copying the first address translation metadata structure into a second memory device thus creating a second address translation metadata structure (Bert, [0054 – In Fig. 4, after steps 420-450, in step 460, processing logic migrates the host metadata objects 246-248 from PMR free space 244 on volatile memory device 140 to the zone namespace 232 on non-volatile memory device 130/second device together using the second write size granularity. Memory region manager 113 can migrate, copy, write, or otherwise move the host metadata objects 246-248 to zone namespace 232 where it can be stored as host metadata 238]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the zone namespace memory of Bert into the memory sub-system namespaces of Harris, for the benefit of using a zone namespace, wherein the address space of the memory device is divided into zones which allows for more efficient management of data as the capacity of the memory device increases (Bert, 0015).
As per Claim 2, the rejection of claim 1 is incorporated, and Harris discloses,
wherein the first memory device comprises a volatile memory device (Harris, [0019 – In Fig. 1, memory subsystem 110 can include a cache or buffer/DRAM/local memory 119 and address circuitry that can receive an address from controller 115 and decode the address to access the memory components/devices 112A to 112N]).
Bert discloses,
wherein the first memory device comprises a volatile memory device (Bert, [0020 – In Fig. 1, volatile memory device 140/DRAM]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the zone namespace memory of Bert into the memory sub-system namespaces of Harris, for the benefit of utilizing the DRAM in the memory sub-system for multiple purposes such as to store the zone namespace metadata and as a buffer for host data, so that the design of the memory sub-system is simplified by preventing the need for additional discrete memory devices (Bert, 0019).
As per Claim 3, the rejection of claim 1 is incorporated, and Harris discloses,
wherein the second memory device comprises a non-volatile memory device (Harris, [0016 - Fig. 1: 112A/second device, NAND flash]; [0016 – In Fig. 1, memory components 112A-112N can include NVM components]).
Bert discloses,
wherein the second memory device comprises a non-volatile memory device (Bert, [0020 - Fig. 1: non-volatile memory device 130]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the zone namespace memory of Bert into the memory sub-system namespaces of Harris, for the benefit of using a zone namespace, wherein the address space of the memory device is divided into zones which allows for more efficient management of data as the capacity of the memory device increases (Bert, 0015).
As per Claim 4, the rejection of claim 1 is incorporated, and Harris discloses,
receiving an instruction reflecting a namespace change associated with a zoned namespace (Harris, [0037 – In Fig. 6, step 605, an instruction to delete a namespace is received. As per Figs. 5A-5B, the instruction to delete the namespace comes from a host]; [0035 – The processing device can receive a request from the host during runtime to delete or deallocate one or more namespaces]; [0024 – In Fig. 3, step 305, the processing device identifies a namespace identifier for a namespace associated with a first write instruction; Since write is associated with update/change, it thereby implies that the write instruction with the namespace identifier is associated with a ZNS]);
wherein the instruction references at least one of a new namespace, a modification to an existing namespace, or a deletion of an obsolete namespace (Harris, [0037 – In Fig. 6, step 605, the processing device removes entries from the namespace table and the L0 table in response to an instruction to delete a namespace. An example of this is shown in Figs. 5A-5B]; [0035 - Figs. 5A-5D show examples of translation tables modified by Fig.1:namespace manager, which enables the host to modify namespaces during runtime. Modifications can include creating/allocating, deleting/deallocating, and resizing namespaces]);
updating the first address translation metadata structure (Harris, [0022 - In Fig. 2, tables 205 and 210 are stored in local memory 119; Also see Figs. 5A-5D with tables 530 and 535 for updates to the first AT metadata structure/first table]) based on the instruction (Harris, [0037 - In response to the instruction to delete a namespace, the processing device removes entries from the namespace table 530 and the L0 table 535]; [0035 - As shown in Fig. 5B, namespace table 520 and L0 table 525 show namespace table 505 and L0 table 510 after processing device deletes namespaces 0 and 2. Upon deletion, the namespace manager rearranges the remaining table entries]; [0025,0026 – In Fig. 3, at step 310, the processing device generates a logical address by combining the namespace ID and namespace offset included in the write/store instruction. At step 315, the processing device translates the logical address to a physical address using a plurality of hierarchical tables; The above citations imply updating the first metadata structure, based on the instruction]);
As per Claim 6, the rejection of claim 1 is incorporated, and Harris discloses,
wherein the first address translation metadata structure (Harris, [Fig. 2]) references a combination of a namespace identifier (Harris, [0011 - A namespace is a contiguous range of logical block addresses/LBAs assigned to one or more systems or processes. A namespace is identified by a namespace identifier/NSID]; [0024 - Namespace identifier is ‘NS 0’ in namespace table 205]) and a logical block address mapped to a physical block address (Harris, [0022 - Fig. 2 shows hierarchical tables including a namespace table 205, wherein tables 205,210,215,220 are used to map logical addresses to physical addresses within memory components 112]; [0026 - The processing device looks up the namespace identifier in namespace table 205. The entry for that namespace includes the starting location and size of the entries for that namespace in table 210, which in turn points to the corresponding entry in table 215, which in turn points to an entry in table 220, the contents of which is the physical address corresponding to the logical block address/LBA composed of the namespace identifier+offset; Since the claim recites ‘a combination of’, the citation is a valid interpretation]).
As per Claim 7, the rejection of claim 1 is incorporated, and Harris discloses,
wherein updating the address translation metadata pointer comprises storing an address (Harris, [0022 – In Fig. 2, each entry in the namespace table 205 includes a starting location/address into the next table in the hierarchy of tables: L0 Table 210; This implies that the address of the first entry is the stored address/pointer referencing the first metadata structure]) referencing the first address translation metadata structure in a hardware register (Harris, [Fig. 1: namespace manager 113]; [0035 - Figs. 5A-5D show examples of translation tables modified/updated by a namespace manager/HW register]).
As per Claim 8, Harris discloses a system (Harris, [0041 – In Fig. 7, computer system 700 corresponds to a host system 120 of Fig. 1 that includes, is coupled to a memory subsystem 110 of Fig. 1]) comprising:
a first memory device (Harris, [Fig. 1: local memory 119, included in controller 115]);
a processing device (Harris, [Fig. 1: processor 117]), operatively coupled with the memory device (Harris, [0020 – In Fig. 1, controller 115 includes processor 117/processing device]), to perform operations comprising:
Bert discloses,
receiving an update instruction (Bert, [0049 – In Fig. 4, step 410, the processing logic receives write/update operations from host 120 including host data objects 234-236 and host metadata objects 246-248. The host data objects 234-236 may have a corresponding write size, implying update associated with ZNS]) reflecting a namespace change associated with a zoned namespace (Bert, [Fig. 2: ZNS 232, NVM 130]; [0017 - A zone namespace memory device has a capacity of 16 TB]) of a plurality of zoned namespaces (Bert, [0044 – In Fig. 3, step 320, the processing logic identifies a first portion of the volatile memory device 140 storing zone namespace metadata 242 corresponding to the zone namespace 232 on NVM 130. ZNS 232 uses a larger write size granularity and enforces sequential writes]);
The remaining limitations are similar to claim 1,4 and therefore the same mappings are incorporated.
As per Claim 9, it is similar to claim 2 and therefore the same mappings are incorporated.
As per Claim 10, it is similar to claim 3 and therefore the same mappings are incorporated.
As per Claim 11, it is similar to claim 4 and therefore the same mappings are incorporated.
As per Claim 13, it is similar to claim 6 and therefore the same mappings are incorporated.
As per Claim 14, it is similar to claim 7 and therefore the same mappings are incorporated.
As per Claim 15, it is similar to claims 1,8 and therefore the same mappings are incorporated.
As per Claim 16, it is similar to claim 2 and therefore the same mappings are incorporated.
As per Claim 17, it is similar to claim 3 and therefore the same mappings are incorporated.
As per Claim 18, it is similar to claim 4 and therefore the same mappings are incorporated.
As per Claim 20, it is similar to claim 6 and therefore the same mappings are incorporated.
Response to Arguments
The Applicant's arguments filed on February 27, 2026 have been fully considered, but they are not persuasive.
In an attempt to overcome the prior art, the amendments recite improper, inconsistent and/or unsupported subject matter.
Applicant argues:‘Claims 1, 7, 8, 14, and 15 have been amended…..the amendments overcome the aledged indefinitness’. (Rem, Pg. 7)
Response: The amendments are incorrect, hence improper. Amendments must be supported by the spec. Whether they are new limitations, updated limitations or canceled limitations, the spec must provide adequate written description support for the addition, update or cancellation.
The present amendments have many issues. For example, as mentioned in the 112(b), amended Claim 1 recites ‘switching’ as two unrelated steps. But Para-0040 of the spec discloses ‘switching’ as one-step.
In amended claim 1, the stored, first table is initially empty. Due to the cancellation, a row of the first table is not updated because the update instruction/request was not received from the host or some other component. So first table stays empty. See the second 112(b).
Claim 1 recites storing an empty first table in DRAM, then copying the empty first table as an empty second table located in NVM, and then updating the pointer which was initially pointing at the empty first table to point to the empty second table. Nowhere does the spec disclose this new ‘copying’ and ‘switching’ mechanism. Claim 1 recites a new invention, new matter. Please see 112(a).
Though claim 1 recites, ‘updating….during address translation operations associated with the plurality of zoned namespaces’, the cancellation prevents any address translation operations, suggesting that the cancellation is improper and unsupported by the spec.
Canceling the two namespace update related limitations in claim 1 and moving them to dependent claim 4 is improper because limitations of claim 4 are not related to claim 1. MPEP § 608.01(m) states that an independent claim is a standalone claim that must contain all the limitations necessary to define the invention. But independent claim 1 does not stand on its own. The cancellation is improper.
The ‘address translation metadata pointer’, is located in controller local DRAM memory 119 and it initially stores the address (points to) of the first table which is located in the DRAM. But after switching this metadata pointer stores the address of the second table located in NVM.
In order to be updated, as required by the spec, the metadata pointer must initially store the address of the first table (update-1) and after switching, it must store the address of the second table (update-2).
Due to the cancellation, amended claim 1 does not recite determining the individual addresses of the first table and the second table. Please see the 112(a).
An excellent online reference on pointers and pointer assignment is:
Stanford CS Education Library - Pointers and Memory, by Nick Parlante
http://cslibrary.stanford.edu/102/PointersAndMemory.pdf
That being said, the combination of Harris,Bert disclose the invention as recited in the spec.
Applicant argues:‘Applicant….submits that the ….references fails to teach…., "switching to the second address translation metadata structure ….." and "updating the address translation metadata pointer to point to the second address translation metadata structure……."’ (Rem, Pg. 7)
Response: This argument is incorrect.
As explained above, the ‘switching’ operation has been misrepresented as two unrelated limitations in amended claim 1. ‘Switching’ is not a toggling action as in a switch (same location). Switching is updating the address of the metadata pointer between two different locations (DRAM and NVM).
Claim 1, submitted as part of the original disclosure and being aligned with the spec, recites the ‘switching’ action via the last limitation (1-step). In other words, the amended limitation, ‘switching to the second address translation metadata structure….’, is redundant and unnecessary as it makes the claim less clear.
However, to align with the spec and overcome the 112(b), the two limitations can be combined. Such as, ‘switching to the second… by updating the address translation metadata pointer to point to….;’.
That said, the combination of Harris, Bert disclose determining the addresses of the first table and the second table. They disclose switching by assigning the address of the second table to the metadata pointer. Please see O/A.
Applicant argues:‘Harris fails…. Because Harris is silent regarding maintaining two separate metadata structures stored on different memory devices, nor does it teach switching between these structures during an update associated with a zoned namespace’. (Rem, Pg. 8)
Response: This argument is incorrect.
The argument mentions, ‘maintaining two separate metadata structures stored on different memory devices’. As recited in claim 1, the two separate metadata structures or tables are empty. The spec does not disclose ‘maintaining’ empty tables in different memory devices.
The spec does not disclose the details of the copy mechanism from DRAM to NVM. This suggests lack of possession, a potential 112(a).
Though the argument mentions, ‘during an update associated with a zoned namespace’, Claim 1 does not recite any table update based on receiving an update instruction. The cancellation of two essential limitations fails to initiate the update of the zoned namespace. Please see related 112(a).
Neither the claim nor the spec recite the significance of ‘zoned namespaces’ with respect to switching. In addition, due to the cancellation, there is no update of any (zoned) namespace. The spec superficially discusses ‘zoned namespaces’. The spec does not disclose the parameters of an update instruction for ZNS. How ZNS is updated and switching is performed, is undisclosed, suggesting lack of possession. Spec Para-0060 recites, ‘The update instruction can reference one or more logical memory address related to one or more namespaces’. Therefore for examination purposes, ‘zoned namespace’ is equivalent to ‘namespace’. That said, Bert discloses ‘zoned namespaces’.
The combination of Harris,Bert disclose the above requirement. Please see O/A.
Examiner Notes:
The prior art made of record and not relied upon is considered pertinent to the applicant's disclosure:
1.‘Dynamic zone group configuration at a memory sub-system’, Micron, US20230266897A1 - The memory sub-system controller can identify a set of zones across one or more memory devices that satisfy a parallelism criterion in view of the size of the initial zone group and can program the set of host data item to memory cells of the identified set of zones. The memory sub-system controller can associate the size of the initial zone group as a fixed zone group size for all zone groups to be managed by the host system.
2.’File system storage allocation based on zones of a memory device’, Micron, US20220244869A1 - When data having locality are written sequentially, the data are written to groups of memory cells that are referred to as zones. Thus, mapping can be recorded at a higher granularity in order to map a particular data group as a zone in the LBA space, which significantly reduces metadata that is logged.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
Prosecution Insights