Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/28/2026 and 8/28/2024 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7 and 9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Dabral (US 20180294230 A1).
Regarding independent claim 1, Dabral teaches a chip comprising: a semiconductor layer (Fig. 1, 101; [0036], "As shown, a stitched die structure 100 may include a semiconductor substrate 101 including a first die area 110A of a first die 104A and a second die area 110B of a second die 104B separate from the first die area 110A."); a first die area in the semiconductor layer (Fig. 1, 110A; [0036], "As shown, a stitched die structure 100 may include a semiconductor substrate 101 including a first die area 110A of a first die 104A and a second die area 110B of a second die 104B separate from the first die area 110A."); a back end of the line (BEOL) build-up structure spanning over the first die area (Fig. 1, 120; [0036], "A back-end-of-the-line (BEOL) build-up structure 120 spans over the first die area 110A and the second die area 110B."), the BEOL build-up structure including a first lower metallic seal around the first die area (Fig. 1, 122A,B; [0036], "In an embodiment, the BEOL build-up structure 120 includes a first metallic seal 122A directly over a first peripheral area of the first die area 110A, a second metallic seal 122B directly over a second peripheral area of the second die area 110B."); a chip-level redistribution layer (RDL) over the BEOL build-up structure, the chip-level RDL including an upper metallic seal along a periphery of the chip (Fig. 1, 122A,B; [0036], "In an embodiment, the BEOL build-up structure 120 includes a first metallic seal 122A directly over a first peripheral area of the first die area 110A, a second metallic seal 122B directly over a second peripheral area of the second die area 110B.", (Treating M_high and M_mid as the RDL and M_low as the BEOL)).
Regarding dependent claim 2, Dabral teaches the chip of claim 1, and further teaches wherein the upper metallic seal at least partially overlies the first lower metallic seal (Fig. 1, 122A,B, (Treating M_High and M_mid as the RDL and M_low as the BEOL, the metallic seals overlap)).
Regarding dependent claim 3, Dabral teaches the chip of claim 1, and further teaches further comprising a second die area in the semiconductor layer (Fig. 1, 110A; [0036], "As shown, a stitched die structure 100 may include a semiconductor substrate 101 including a first die area 110A of a first die 104A and a second die area 110B of a second die 104B separate from the first die area 110A.").
Regarding dependent claim 4, Dabral teaches the chip of claim 3, and further teaches wherein the BEOL build-up structure includes a second lower metallic seal around the second die area (Fig. 1, 122A,B; [0036], "In an embodiment, the BEOL build-up structure 120 includes a first metallic seal 122A directly over a first peripheral area of the first die area 110A, a second metallic seal 122B directly over a second peripheral area of the second die area 110B.").
Regarding dependent claim 5, Dabral teaches the chip of claim 4, and further teaches wherein the upper metallic seal at least partially overlies the first lower metallic seal and the second lower metallic seal (Fig. 1, 122A,B, (Treating M_High and M_mid as the RDL and M_low as the BEOL, the metallic seals overlap)).
Regarding dependent claim 6, Dabral teaches the chip of claim 4, and further teaches wherein the chip-level RDL includes a plurality of die area-to-die area interconnects electrically connected between the first die area and the second die area (Fig. 1, 132, 134, 122A,B; [0037], "In accordance with embodiments, the die routing 135 may be formed from one or more vias 132 and metal layers 134 within the BEOL build-up structure 120. ").
Regarding dependent claim 7, Dabral teaches the chip of claim 6, and further teaches wherein the plurality of die area-to-die area interconnects spans over a first portion of the first lower metallic seal and second portion of the second lower metallic seal (Fig. 1, 132, 134, 122A,B; [0037], "In accordance with embodiments, the die routing 135 may be formed from one or more vias 132 and metal layers 134 within the BEOL build-up structure 120. ", (The lines pass span over the seals)).
Regarding dependent claim 9, Dabral teaches the chip of claim 3, and further teaches wherein the BEOL build-up structure includes: a first group of first contact pads electrically connected with the first die area; a second group of second contact pads electrically connected with the second die area (Fig. 1, 140; [0036], "The BEOL build-up structure 120 may additionally include a plurality of contact pads 140 such as, but not limited to, under bump metallurgy pads, which may be electrically connected to the first and second die 104A, 104B, and optionally the metallic seals 122A, 122B.").
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 and 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dabral (US 20180294230 A1), in view of Pietambram (US 20190189563 A1).
Regarding dependent claim 8, Dabral teaches the chip of claim 7. However, Dabral does not teach wherein the BEOL build-up structure includes a first group of first contact pads electrically connected with the first die area and a second group of second contact pads electrically connected with the second die area, and the plurality of die area-to-die area interconnects connects first group of first contact pads and the second group of second contact pads.
However, in the same field of endeavor, Pietambaram teaches wherein the BEOL build-up structure includes a first group of first contact pads electrically connected with the first die area and a second group of second contact pads electrically connected with the second die area (Fig. 17, 110; [0053], "Also note, that each die pad (e.g. die pad 110 of FIG. 17) of dies 1105-106 is coupled to at least one of the first VHD conductive lines 1805."), and the plurality of die area-to-die area interconnects connects first group of first contact pads and the second group of second contact pads (Fig. 18, 1805; [0053], "Also note, that each die pad (e.g. die pad 110 of FIG. 17) of dies 1105-106 is coupled to at least one of the first VHD conductive lines 1805.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the chip of Dabral with the pads and interconnects of Pietambaram so as to "enable fine die-to-die interconnects", (Pietambaram, [0051]).
Regarding dependent claim 10, Dabral teaches the chip of claim 9. However, Dabral does not teach wherein the chip-level RDL includes a plurality of die area-to-die area interconnects electrically connected between the first group of first contact pads and the second group of second contact pads.
However, in the same field of endeavor, Pietambaram teaches wherein the chip-level RDL includes a plurality of die area-to-die area interconnects electrically connected between the first group of first contact pads and the second group of second contact pads (Fig. 18, 1805; [0053], "Also note, that each die pad (e.g. die pad 110 of FIG. 17) of dies 1105-106 is coupled to at least one of the first VHD conductive lines 1805.").
Regarding dependent claim 11, Dabral, as previously modified by Pietambaram, teaches the chip of claim 10. However, as previously combined, they do not teach wherein the plurality of die area-to-die area interconnects in the chip-level RDL is embedded within one or more organic dielectric layers.
However, Pietambaram further teaches wherein the plurality of die area-to-die area interconnects in the chip-level RDL is embedded within one or more organic dielectric layers (Fig. 18, 1801a-c; [0051], "For some embodiments, VHD dielectric layers 1801a-c may be a polymer material, such as, for example, polyimide, epoxy or build-up film (BF).").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the chip as described by the combination of Dabral and Pietambaram with the organic dielectric layer of Pietambaram so as to "provide a VHD interconnect layer that enables fine die-to-die interconnections and high density routing", (Pietambaram, [0047]).
Regarding dependent claim 12, Dabral, as previously modified by Pietambaram, teaches the chip of claim 11, and further teaches wherein the BEOL build-up structure includes inorganic dielectric layers (Fig. 4D, 412, 414; [0046], "...followed by a conformal deposition of one or more barrier layers 412, 414. Exemplary barrier layers include, but are not limited to, inorganic materials such as oxides (e.g. SiO.sub.2, Al.sub.2O.sub.3, etc.) and nitrides (e.g. silicon nitride, etc.).").
Claim(s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dabral (US 20180294230 A1), in view of Pietambram (US 20190189563 A1) and Yu (US 20190148274 A1).
Regarding dependent claim 13, Dabral, as previously modified by Pietambaram, teaches the chip of claim 11. However, as previously combined, they do not teach wherein the BEOL build-up structure includes a passivation layer, a first plurality of first openings in the passivation layer exposing the first group of first contact pads, and a second plurality of second openings in the passivation layer exposing the second group of second contact pads.
However, in the same field of endeavor, Yu teaches wherein the BEOL build-up structure includes a passivation layer, a first plurality of first openings in the passivation layer exposing the first group of first contact pads, and a second plurality of second openings in the passivation layer exposing the second group of second contact pads (Fig. 9, 113, 115, 111; [0021], "In some embodiments, the openings 115 are formed in the passivation layer 113 to expose portions of the contact pads 111.", (As shown here and in Fig. 20, there are two dies, and so two groups of openings and contact pads)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the chip as described by the combination of Dabral and Pietambaram with the passivation layer and openings of Yu so as to "to further reduce the physical size" of the device, (Yu, [0004]).
Regarding dependent claim 14, Dabral, as previously modified by Pietambaram and Yu, teaches the chip of claim 13. However, as previously combined, they do not teach wherein the plurality of die area-to-die area interconnects includes a first plurality of first vias directly on the first group of first contact pads.
However, Pietambaram further teaches wherein the plurality of die area-to-die area interconnects includes a first plurality of first vias directly on the first group of first contact pads (Fig. 18, 141, 142; [0053], "Continuing with FIG. 18, first VHD conductive lines 1805 are coupled to first VHD conductive pillars 141 by the one or more top surfaces exposed on first VHD dielectric layer 1801a. Also note, that each die pad (e.g. die pad 110 of FIG. 17) of dies 1105-106 is coupled to at least one of the first VHD conductive lines 1805. For another embodiment, second VHD conductive pillars 142 are formed over first VHD conductive lines 1805.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the chip as described by the combination of Dabral, Pietambaram, and Yu with the vias of Pietambaram so as to "enable fine die-to-die interconnects", (Pietambaram, [0051]).
Regarding dependent claim 15, Dabral, as previously modified by Pietambaram and Yu, teaches the chip of claim 14. However, as previously combined, they do not teach wherein each first via has a perimeter that is smaller than a corresponding first opening.
However, Pietambaram further teaches wherein each first via has a perimeter that is smaller than a corresponding first opening ([0065], "Accordingly, for some embodiments, the width of via opening 2122 may be at least the minimum line width L plus twice the misalignment for the lithographic patterning process.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the chip as described by the combination of Dabral, Pietambaram, and Yu with the difference in perimeter sizes of Pietambaram so as "to account for any misalignment", (Pietambaram, [0065]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20190237430 A1, pertaining to a device with a redistribution layer and BEOL.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY JAMES MATTABONI whose telephone number is (571)270-0766. The examiner can normally be reached Monday-Friday 9 AM - 5 PM.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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