Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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Fig. 2 of the instant application, reproduced with annotations added by the examiner.
Drawings
Figure 1A should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the presence of P-doped must be shown or the features canceled from the claims. No new matter should be entered.
The drawings are objected to because the "fish .
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 3 is objected to as it is dependent directly on claim 1, but separates claim 4 from claim 2, which claim 4 is dependent on.
Claim 17 is objected to because of the following informality: in line 3, “covering lower half” should be “covering a lower half”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7, 11-12, 16, and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation, “a second via”. However, no first via is recited in either this claim or any of its parent claims, claims 1 and 6, thus creating confusion over whether an additional via needs to be present.
Claim 11 recites the limitations, “forming a first N-well region below the set of P-type doped regions and the set of N-type doped regions on a first side of the spacer liner and the STI; and forming a second N-well region below the set of P-type doped regions and the set of N-type doped regions on a second side of the spacer liner and the STI.” It is unclear whether the set of doped regions that the first N-well is formed under is the same set of doped regions as the one the second N-well is formed under, or if they are the same region.
Claim 12 is dependent on claim 11 and therefore inherits the deficiencies of its parent claim.
Claim 16 recites the limitation, “a second via”. However, no first via is recited in either this claim or any of its parent claims, claims 10, 14, and 15, thus creating confusion over whether an additional via needs to be present.
Claim 19 recites the limitation, “and the second N-well region.”, at the end of the claim. This appears to be an incomplete clause, and therefore it is uncertain what additional limitation was intended to be recited here.
Claim 20 is dependent on claim 19 and therefore inherits the deficiencies of the parent claim.
The following will be assumed for examination purposes:
The second vias recited in claims 7 and 16 are the only vias required to be present.
The missing part of the last limitation in claim 19 was meant to be “is located on a second side of the spacer liner and the STI.”
These rejections may be overcome by:
Either reciting a first via in either claims 7 and 16 or in one of their respective parent claims, or by renaming the second via to the first via.
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Fig. 18A of Yu, reproduced inverted and with annotations added by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 17 is rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Yu et. al., Pub. No. US 2022/0069117, hereafter referred to as Yu.
Regarding claim 17, Yu discloses all of the limitations of the claim in Fig. 18A, reproduced above with annotations added by the examiner: “A semiconductor device” (Fig. 18A), “comprising: a backside contact” ([0041]; Fig. 18A, backside source contact 270); “a spacer liner covering lower half of sidewalls of the backside contact” ([0042]; Fig. 18A, note that the liner 276 covers the entirety of the sidewalls of the backside source contact 270, and thus covers the lower halves); “and an N-well region connected to the spacer liner so that the spacer liner isolates the N-well region from contact with the backside contact” ([0028]: “In some instances, the dummy epitaxial feature 238 may be doped with an n-type dopant…”; Fig. 18A, note that the dummy epitaxial feature 238 contacts the liner 276, which also helps to isolate the dummy epitaxial feature 238 from the backside source contact 270), “wherein: the spacer liner is made of a high-k dielectric material” ([0042]: “The liner 276 may include silicon nitride.”), “the N-well region is electrically connected to a voltage source/drain supply” ([0028], [0030], [0035]; Fig. 18A, note that the frontside drain contact 280 is connected to the drain feature 242D, which is in turn connected to the dummy epitaxial feature 238; note also that it is inherent to the drain contact 280 that it will be supplied with a voltage), “and the backside contact is connected to a voltage drain/source supply or to a ground voltage” ([0041]; Fig. 18A, note that it is inherent to the backside source contact 270 that it will be supplied with a voltage).
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Fig. 1 of Nam, reproduced with annotations added by the examiner.
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Fig. 3 of Nam, reproduced with annotations added by the examiner.
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Fig. 4 of Nam, reproduced with annotations added by the examiner.
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Fig. 5 of Nam, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 5-10, and 13-16 is rejected under 35 U.S.C. 103 as being unpatentable over Nam et. al., Pub. No. US 2025/0056838, hereafter referred to as Nam, in view of Yu.
Regarding claim 1, Nam teaches “A semiconductor device” (Nam Fig. 1), “comprising: a passive device” (Nam [0028]; Fig. 1, first region R1), “comprising: a first backside contact” (Nam [0027]; Fig. 4, first backside contact 70); “a shallow trench isolation (STI) above the first backside contact” (Nam [0047]; Fig. 4, combination of field insulating layer 105 and first back interlayer insulating layer 110) “and covering a top surface and an upper half of sidewalls of the first backside contact” (Nam Fig. 4, note that the field insulator 105 and the first back interlayer insulating layer 110 cover the top surface and upper half of the sidewalls of the first backside contact 70); and “an interconnection layer covering a bottom surface of the first backside contact” (Nam [0105]; Fig. 5, first back wiring line 50 and first back wiring via 55).
Nam, however, does not teach “a spacer liner covering a lower half of the sidewalls of the first backside contact”.
Yu, on the other hand, does teach “a spacer liner covering a lower half of the sidewalls of the first backside contact” (Yu [0041-0042]; Fig. 18A, note that the liner 276 covers the side walls of the backside source contact 270).
The dielectric barrier layer of Yu can be incorporated into the device of Nam by disposing a dielectric liner along the side walls of the first backside contact.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to dispose a dielectric liner over the side walls of the first backside contact of Nam as suggested by Yu because doing so would provide further insulation of the first backside contact from other components of the device and it would be a simple combination of elements of the two disclosures.
Regarding claim 3, the combination of Nam and Yu described in the discussion of claim 1 teaches “The semiconductor device of claim 1” but does not teach “wherein the spacer liner is made of a high-k dielectric material.”
Yu, on the other hand, anticipates “wherein the spacer liner is made of a high-k dielectric material” by teaching that the liner can be made from silicon nitride, which is known to be a high-k dielectric material ([0042]: “The liner 276 may include silicon nitride.”).
The use of silicon nitride as the material for the dielectric barrier layer of Yu can be incorporated into the combined device of Nam and Yu described in the discussion of claim 1 by making the dielectric barrier layer of said combined device out of silicon nitride.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have used silicon nitride as the material for the dielectric barrier layer in the combined device of Nam and Yu described in the discussion of claim 1 because it is able to serve the purpose of an insulating material and it would be a simple substitution of one material for another.
Regarding claim 5, the combination of Nam and Yu described in the discussion of claim 1 further teaches “The semiconductor device of claim 1, wherein the passive device is electrically connected to a back end of line (BEOL)” (Nam [0026]; Fig. 4, front wiring line 207 within the first region R1; also see Fig. 1 and note that the cross section B1-B1 passes through the first region R1) “through a first via” (Nam [0026]; Fig. 4, front wiring via 206 within the first region R1; also see Fig. 1 and note that the cross section B1-B1 passes through the first region R1).
Regarding claim 6, the combination of Nam and Yu described in the discussion of claim 1 further teaches “The semiconductor device of claim 1, further comprising: an active device” (Nam [0028]; Fig. 1, second region R2), “comprising: source/drain regions” (Nam [0027]; Fig. 5, second source/drain pattern 250 and fourth source/drain pattern 450); “gate regions” (Nam [0027]: “The semiconductor device may include… a plurality of gate electrodes 120…”; Fig. 1, gate electrodes 120 in the second region R2); “and a second backside contact” (Nam [0027]; Fig. 4, second buried conductive pattern 80).
Regarding claim 7, the combination of Nam and Yu as applied to claim 1 above further teaches “The semiconductor device of claim 6, wherein the active device is electrically connected to a back end of line (BEOL)” (Nam [0026]; Fig. 4, front wiring line 207 within the second region R2; also see Fig. 1 and note that the cross section B2-B2 passes through the second region R2) “through a second via” (Nam [0026]; Fig. 4, front wiring via 206 within the second region R2; also see Fig. 1 and note that the cross section B2-B2 passes through the second region R2).
Regarding claim 8, the combination of Nam and Yu as applied to claim 1 above further teaches “The semiconductor device of claim 6, wherein the active device further comprises alternative layers extended horizontally between two adjacent source/drain regions” (Nam [0030]; Fig. 3, note that some of the second sheet patterns NS2 are disposed horizontally between two adjacent source/drain patterns 250).
Regarding claim 9, the combination of Nam and Yu as applied to claim 1 above further teaches “The semiconductor device of claim 8, wherein the alternative layers include silicon” (Nam [0167]: “In some implementations, each of the sheet patterns NS1, NS2, NS3, and NS4 (see FIGS. 2 and 3) may include… silicon…”).
Regarding claim 10, Nam teaches “A method of fabricating a semiconductor device” (Nam Fig. 1), “the method comprising: forming a passive device” (Nam [0028]; Fig. 1, first region R1) “comprising: forming a first backside contact” (Nam [0027]; Fig. 4, first backside contact 70); “forming a shallow trench isolation (STI) above the first backside contact” (Nam [0047]; Fig. 4, combination of field insulating layer 105 and first back interlayer insulating layer 110) “and covering a top surface and an upper half of sidewalls of the first backside contact” (Nam Fig. 4, note that the field insulator 105 and the first back interlayer insulating layer 110 cover the top surface and upper half of the sidewalls of the first backside contact 70); and “forming an interconnection layer covering a bottom surface of the first backside contact” (Nam [0105]; Fig. 5, first back wiring line 50 and first back wiring via 55).
Nam, however, does not teach “forming a spacer liner covering a lower half of the sidewalls of the first backside contact”.
Yu, on the other hand, does teach “forming a spacer liner covering a lower half of the sidewalls of the first backside contact” (Yu [0041-0042]; Fig. 18A, note that the liner 276 covers the side walls of the backside source contact 270).
The formation of a dielectric barrier layer of Yu can be incorporated into the process of Nam by disposing a dielectric liner along the side walls of the first backside contact.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to dispose a dielectric liner over the side walls of the first backside contact of Nam as suggested by Yu because doing so would provide further insulation of the first backside contact from other components of the device and it would be a simple combination of elements of the two disclosures.
Regarding claim 13, the combination of Nam and Yu described in the discussion of claim 10 further teaches “The method of claim 10, further comprising establishing an electrical connection between the passive device and a back end of line (BEOL)” (Nam [0026]; Fig. 4, front wiring line 207 within the first region R1; also see Fig. 1 and note that the cross section B1-B1 passes through the first region R1) “through a first via” (Nam [0026]; Fig. 4, front wiring via 206 within the first region R1; also see Fig. 1 and note that the cross section B1-B1 passes through the first region R1).
Regarding claim 14, the combination of Nam and Yu described in the discussion of claim 10 further teaches “The method of claim 10, further comprising: forming an active device” (Nam [0028]; Fig. 1, second region R2), “comprising: forming source/drain regions” (Nam [0027]; Fig. 5, second source/drain pattern 250 and fourth source/drain pattern 450); “forming gate regions between the source/drain regions” (Nam [0027]: “The semiconductor device may include… a plurality of gate electrodes 120…”; Fig. 1, gate electrodes 120 in the second region R2; also see [0054] and Fig. 3 and note that some of the inner gate structures I_GS are formed between source/drain patterns 250); “and forming a second backside contact below one of the source/drain regions” (Nam [0027]; Fig. 4, second buried conductive pattern 80).
Regarding claim 15, the combination of Nam and Yu as applied to claim 10 above further teaches “The method of claim 14, further comprising forming alternative layers extended horizontally between two adjacent source/drain regions” (Nam [0030]; Fig. 3, note that some of the second sheet patterns NS2 are disposed horizontally between two adjacent source/drain patterns 250).
Regarding claim 16, the combination of Nam and Yu as applied to claim 10 above further teaches “The method of claim 15, further comprising establishing an electrical connection between the active device and a back end of line (BEOL)” (Nam [0026]; Fig. 4, front wiring line 207 within the second region R2; also see Fig. 1 and note that the cross section B2-B2 passes through the second region R2) “through a second via” (Nam [0026]; Fig. 4, front wiring via 206 within the second region R2; also see Fig. 1 and note that the cross section B2-B2 passes through the second region R2).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Nam.
Regarding claim 18, Yu teaches “The semiconductor device of claim 17, further comprising: a shallow trench isolation (STI) above the backside contact” (Yu [0041-0042]; Fig. 18A, note that portions of the backside dielectric layer 278 are disposed above portions of the backside source contact 270 in the inverted view shown above) “and covering a top surface and an upper half of sidewalls of the backside contact” (Yu [0041-0042]; Fig. 18A, note that the backside dielectric layer 278 covers the top surfaces and sidewalls of the backside source contact 270 in the inverted view shown above), but does not teach “an interconnection layer covering a bottom surface of the backside contact.”
Nam, on the other hand, does teach “an interconnection layer covering a bottom surface of the backside contact” (Nam [0105]; Fig. 5, first back wiring line 50 and first back wiring via 55; note that the first back wiring line 50 covers the first backside contact 70).
The back wiring line of Nam can be incorporated into the device of Yu as a similar back wiring line that covers the backside source contact.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have incorporated a back wiring line into the device of Yu as taught by Nam because the back wiring line can provide a voltage to the backside source contact and it would be a simple combination of elements of the two disclosures.
Allowable Subject Matter
Claims 2 and 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, whether alone or in combination, especially when all claim limitations are considered, fails to teach or suggest the limitations of:
Claim 2, which teaches “a set of P-type doped regions and a set of N-type doped regions on opposite sides of the ILD; and a first N-well region and a second N-well region below the set of P-type doped regions and the set of N-type doped regions, wherein: the first N-well region is located on a first side of the spacer liner and the STI, and the second N-well region is located on a second side of the spacer liner and the STI.”
Claim 4 is dependent on claim 2 and therefore contains the same allowable material.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert E Throckmorton whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Monday to Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.E.T./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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