DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/29/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “signal output unit” in claims 1, 7 and 10.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. US 2019/0327438.
Re claim 11, Kim discloses an image sensing device (CMOS image sensor – figure 1) comprising: a ramp generation circuit (30) (figure 1; paragraphs 28-37) including: a ramp source follower transistor configured to output a ramp output signal to an output node by amplifying a voltage of a transfer node, to which a ramping voltage changes according to a first slope or a second slope is applied; and a ramp switch configured to selectively connect the transfer node to the output node (slope control block 610 includes analog buffer 613 implemented using ramp switches and a source follower circuit for controlling slope of a ramp signal generator) (figures 6,7; paragraphs 56-64); and an analog-to-digital converter (ADC) configured to generate image data by comparing the ramp output signal with a pixel signal output from a pixel configured to sense an incident light (CMOS image sensor includes a ramp signal generator 30 and a slope analog-to-digital converter to output digital pixel signals and sense incident light)(figure 1; paragraphs 28-37).
Re claim 16, Kim further discloses that the ramp source follower transistor is further configured to generate, based on the ramping voltage, the ramp output signal changing according to one of the first and second slopes, and the ramp source follower transistor outputs the ramp output signal through a single path (analog buffer 613 outputs a ramp signal having variable slopes) (figures 6-7; paragraphs 56-64).
Re claim 17, Kim discloses a method for operating an image sensing device (CMOS image sensor – figure 1), the method comprising: generating first image data by comparing a ramp output signal, which changes according to a first slope, with a pixel signal output from a pixel configured to sense an incident light; electrically connecting an output node, through which the ramp output signal is output, to a gate of a ramp source follower transistor configured to generate the ramp output signal; and generating second image data by comparing the ramp output signal, which changes according to a second slope different from the first slope, with the pixel signal (analog buffer 613 includes a source follower transistor and outputs a ramp signal having variable slopes) (figures 6-7; paragraphs 56-64).
Re claim 18, Kim further discloses that the first slope is greater than the second slope when the pixel signal is a reference signal generated in a state that a sensing node of the pixel is reset (slope control block 610 includes a voltage generation unit for generating controllable reference voltage for generating slopes having different values) (figures 6,7; paragraphs 56-64).
Re claim 19, Kim further discloses wherein the first slope is less than the second slope when the pixel signal is an image signal generated in a state that photocharges generated by the pixel are accumulated in a sensing node of the pixel (slope control block 610 including a voltage generation unit for generating controllable reference voltage for generating slopes having different value) (figures 6,7; paragraphs 56-64).
Re claim 20, Kim further discloses setting, after the electrically connecting, a voltage level of the ramp output signal to be higher than a voltage level of the pixel signal (ramp voltage level may increase to a point where it is higher than a voltage level of the pixel signal and when the ramp voltage matches pixel signal at a point in time comparison signal values are inverted) (figures 2A, 2B; paragraphs 34 and 39-43).
Allowable Subject Matter
Claims 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Re claims 12-14, the prior art fails to teach or suggest, an image sensing device having the specific configurations disclosed in claims 12-14, wherein image sensing device comprises: a ramp generation circuit including: a ramp source follower transistor configured to output a ramp output signal to an output node by amplifying a voltage of a transfer node, to which a ramping voltage changes according to a first slope or a second slope is applied; and a ramp switch configured to selectively connect the transfer node to the output node; and an analog-to-digital converter (ADC) configured to generate image data by comparing the ramp output signal with a pixel signal output from a pixel configured to sense an incident light, wherein the ADC includes: a comparator configured to generate comparison data by comparing the ramp output signal with the pixel signal; a first switch configured to selectively connect a non-inverting input terminal of the comparator to an inverting output terminal of the comparator; a second switch configured to selectively connect an inverting input terminal of the comparator to a non-inverting output terminal of the comparator; and a counter configured to generate the image data by counting the comparison data. The examiner notes that the specific arrangement and configuration of the imaging sensing device and ramp generation circuit disclosed in the specification and claimed in the claims is not disclosed by the prior art.
Re claim 15, the prior art fails to teach or suggest, an image sensing device having the specific configurations disclosed in claim 15, wherein image sensing device comprises: a ramp generation circuit including: a ramp source follower transistor configured to output a ramp output signal to an output node by amplifying a voltage of a transfer node, to which a ramping voltage changes according to a first slope or a second slope is applied; and a ramp switch configured to selectively connect the transfer node to the output node; and an analog-to-digital converter (ADC) configured to generate image data by comparing the ramp output signal with a pixel signal output from a pixel configured to sense an incident light, wherein the ramp switch selectively connects the transfer node to the output node in response to a ramp auto-zeroing signal, which has a logic high level before a slope of the ramp output signal changes between the first and second slopes. The examiner notes that the specific arrangement and configuration of the imaging sensing device and ramp generation circuit disclosed in the specification and claimed in the claims is not disclosed by the prior art.
Claims 1-10 are allowed.
The following is an examiner’s statement of reasons for allowance:
Re claims 1-10, the prior art fails to teach or suggest, a ramp generation circuit having the specific configurations disclosed in claims 1-10, wherein the ramp generation circuit comprises: a ramping voltage generator configured to generate a ramping voltage that changes according to a first slope or a second slope; a blocking capacitor configured to transmit the ramping voltage to a transfer node; a signal output unit configured to amplify a voltage of the transfer node to output a ramp output signal to an output node; and a ramp switch configured to selectively connect the transfer node to the output node. The examiner notes that the specific arrangement and configuration of the ramp generation circuit disclosed in the specification and claimed in the claims is not disclosed by the prior art.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bae US 2022/0247890 discloses an analog-to-digital conversion circuit for a pixel array including a ramp voltage generator.
Liu US 2019/0394415 discloses an image sensor circuit including a ramp signal generator.
Milkov US 2016/0118992 discloses a comparator circuit for use in a column-parallel single-slope analog-to-digital converter.
Jun US 2024/0147092 discloses an imaging apparatus including an analog-to-digital converter and ramp signal generation circuit.
Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kelly L. Jerabek whose telephone number is (571) 272-7312. The examiner can normally be reached on Monday - Friday (8:00 AM - 5:00 PM).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, George Eng can be reached at (571) 272-7495. The fax phone number for submitting all Official communications is (571) 273-7300. The fax phone number for submitting informal communications such as drafts, proposed amendments, etc., may be faxed directly to the Examiner at (571) 273-7312.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice .
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/KELLY L JERABEK/Primary Examiner, Art Unit 2699