DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 15/466,347, filed on 06/26/2017.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/29/24 has been considered by the examiner.
Drawings
The drawings were received on 08/29/24 are acceptable.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1-20 are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-20 of prior U.S. Patent No. 12,079,018. This is a statutory double patenting rejection.
US Application No. 18/818,651
US Patent No. 12,079,018
Claim 1. A semiconductor device comprising: a first circuit; and a voltage regulator electrically connected to the first circuit and including: a first terminal; a second terminal; a third terminal; a second circuit electrically connected to the first and second terminals, including a first transistor, and configured to operate on a basis of a first voltage and a second voltage both provided to the second circuit, the first voltage being proportional to a third voltage on the third terminal; a second transistor electrically connected to the first and third terminals; and a third circuit including a third transistor and configured to control the second transistor to turn on or turn off on a basis of current flowing through the third transistor, the current flowing through the third transistor corresponding to current flowing through the first transistor, the current flowing through the first transistor varying on a basis of a difference between the first and second voltages.
Claim 1. A semiconductor device comprising: a first circuit; and a voltage regulator connected to the first circuit and including: a first terminal; a second terminal; a third terminal; a second circuit between the first and second terminals, including a first transistor, and configured to operate based on first and second voltages both provided to the second circuit; a second transistor between the first and third terminals; and a third circuit including a third transistor and configured to control on and off of the second transistor based on current flowing through the third transistor, wherein the current flowing through the third transistor corresponds to current flowing through the first transistor, and the current flowing through the first transistor varies based on a difference between the first and second voltages, the second voltage being proportional to a third voltage of the third terminal.
Claim 2. The semiconductor device according to claim 1, wherein the third transistor is directly connected to the first terminal.
Claim 2. The semiconductor device according to claim 1, wherein the third transistor is directly connected to the first terminal.
Claim 3. The semiconductor device according to claim 1, wherein the third transistor is directly connected to the second terminal.
Claim 3. The semiconductor device according to claim 1, wherein the third transistor is directly connected to the second terminal.
Claim 4. The semiconductor device according to claim 1, wherein the second circuit includes a differential amplifier circuit.
Claim 4. The semiconductor device according to claim 1, wherein the second circuit includes a differential amplifier circuit.
Claim 5. The semiconductor device according to claim 1, wherein the second circuit include an operational amplifier circuit.
Claim 5. The semiconductor device according to claim 1, wherein the second circuit include an operational amplifier circuit
Claim 6. The semiconductor device according to claim 1, wherein the third transistor is electrically connected to both the first and second terminals.
Claim 6. The semiconductor device according to claim 1, wherein the third transistor is electrically connected to both the first and second terminals.
Claim 7. The semiconductor device according to claim 1, wherein the third circuit further comprises a fourth transistor, and the fourth transistor is configured to switch a state of the second transistor between a conductive state and a non-conductive state.
Claim 7. The semiconductor device according to claim 1, wherein the third circuit further comprises a fourth transistor, and the fourth transistor is configured to switch a state of the second transistor between a conductive state and a non-conductive state.
Claim 8. The semiconductor device according to claim 7, wherein the third transistor is electrically connected to a gate of the fourth transistor.
Claim 8. The semiconductor device according to claim 7, wherein the third transistor is electrically connected to a gate of the fourth transistor.
Claim 9. The semiconductor device according to claim 7, wherein the fourth transistor is configured to switch the state of the second transistor based on a signal corresponding to the current flowing through the third transistor.
Claim 9. The semiconductor device according to claim 7, wherein the fourth transistor is configured to switch the state of the second transistor based on a signal corresponding to the current flowing through the third transistor.
Claim 10. The semiconductor device according to claim 7, wherein the fourth transistor is electrically connected to a gate of the second transistor.
Claim 10. The semiconductor device according to claim 7, wherein the fourth transistor is electrically connected to a gate of the second transistor
Claim 11. The semiconductor device according to claim 10, wherein the fourth transistor is electrically connected to the first terminal.
Claim 11. The semiconductor device according to claim 10, wherein the fourth transistor is electrically connected to the first terminal.
Claim 12. The semiconductor device according to claim 10, wherein the fourth transistor is electrically connected to the second terminal.
Claim 12. The semiconductor device according to claim 10, wherein the fourth transistor is electrically connected to the second terminal.
Claim 13. The semiconductor device according to claim 1, further comprising: a fourth terminal to which the second voltage is configured to be supplied.
Claim 13. The semiconductor device according to claim 7, wherein the third transistor is electrically connected to both the first and second terminal
Claim 14. The semiconductor device according to claim 1, wherein the second circuit is configured to output a signal to the second transistor
Claim 14. The semiconductor device according to claim 1, wherein the second circuit is configured to output a signal to the second transistor.
Claim 15. The semiconductor device according to claim 1, further comprising: a fourth circuit configured to supply, as a feedback voltage, the first voltage to the second circuit.
Claim 15. The semiconductor device according to claim 1, further comprising: a fourth circuit configured to supply, as a feedback voltage, the second voltage to the second circuit.
Claim 16. The semiconductor device according to claim 15, wherein the fourth circuit includes a voltage-dividing circuit and is connected to the second transistor and the second terminal.
Claim 16. The semiconductor device according to claim 15, wherein the fourth circuit includes a voltage-dividing circuit and is connected to the second transistor and the second terminal.
Claim 17. The semiconductor device according to claim 15, wherein the fourth circuit includes a plurality of resistors.
Claim 17. The semiconductor device according to claim 15, wherein the fourth circuit includes a plurality of resistors.
Claim 18. The semiconductor device according to claim 17, wherein the plurality of resistors comprises a first resistor and a second resistor connected to each other in series, the first resistor is directly connected to the second terminal, and the second resistor is directly connected to the third terminal.
Claim 18. The semiconductor device according to claim 17, wherein the plurality of resistors comprises a first resistor and a second resistor connected to each other in series, the first resistor is directly connected to the second terminal, and the second resistor is directly connected to the third terminal.
Claim 19. The semiconductor device according to claim 18, wherein a node that connects the first and second resistors to each other has a voltage level of the feedback voltage supplied to the second circuit.
Claim 19. The semiconductor device according to claim 18, wherein a node that connects the first and second resistors to each other has a voltage level of the feedback voltage supplied to the second circuit.
Claim 20. The semiconductor device according to claim 19, wherein the second circuit includes a fifth transistor connected to the first transistor, and the feedback voltage is supplied directly to a gate of the fifth transistor.
Claim 20. The semiconductor device according to claim 19, where in the second circuit includes a fifth transistor connected to the first transistor, and the feedback voltage is supplied directly to a gate of the fifth transistor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang et al. (US 9,104,223 B2) disclose an output voltage variation reduction.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADOLF D BERHANE whose telephone number is (571)272-2077. The examiner can normally be reached 7:00 AM to 4:00 PM.
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/ADOLF D BERHANE/Primary Examiner, Art Unit 2838