DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 10 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ravi et al, "A 2.4-GHz 20 40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, Vol. 47, no. 12, December 1, 2012, (2012-12-01), pages 3184-3196, XP011485416, ISSN: 0018-9200, D(OI: 10.1109/JSSC.2012.2216671; hereinafter Ravi).
Regarding claim 10, Ravi discloses a method to generate a transmit signal, the method comprising: generating a first modulated local oscillator signal (s1(t)) and a second modulated local oscillator signal (s2(t)) such that the second modulated local oscillator signal (s2(t)) has a delay to the first modulated local oscillator signal (s1(t)) (the second modulated LO signal is dynamically delayed in the phase modulator that output signal s2(t); Fig. 5; pg. 3, col 1, line 4 – col 2, line 44); triggering a first amplifier (upper amplifier of PA module) by the first modulated local oscillator signal (s1(t)); triggering second amplifier (lower amplifier of PA module) by the second modulated local oscillator signal (s2(t)) pg. 3, col 2, lines 33-36); and
combining the signal output from the first amplifier and the signal output from the second amplifier (the two outphasing signals from the upper amplifier and the lower amplifier are then combined in a combiner; Fig. 5; pg. 3, col 2, lines 36-37).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Ravi et al, "A 2.4-GHz 20 40-MHz Channel WLAN Digital Out-phasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS", IEEE Journal of Solid State Circuits, IEEE, USA, vol. 47, no. 12, December 1, 2012, (2012-12-01), pages 3184-3196, XP011485416, ISSN: 0018-9200, DOI: 10.1109/JSSC.2012.2216671; hereinafter Ravi) in view of Gross et al (US 2022/0,338,148; hereinafter Gross).
Regarding claim 1, Ravi discloses a transmitter (Fig. 5), comprising:
a first amplifier (upper amplifier of PA module) coupled to a first modulated local oscillator signal (s1(t)) (pg. 3, col 1, line 4 – col 2, line 44);
a second amplifier (lower amplifier of PA module) coupled to a second modulated local oscillator signal (s2(t)) (pg. 3, col 2, lines 10-44);
digital to time conversion circuitry configured to generate the first modulated local oscillator signal and the second modulated local oscillator signal such that the second modulated local oscillator signal has a delay to the first modulated local oscillator signal (the second modulated LO signal is dynamically delayed in the phase modulator that output signal s2(t) using delayed based wideband digital modulation; pg. 2, col 2, line 32 - pg. 3, col 2, line 44; pg. 7, col 1, lines 19 – pg. 7, col 2, line 42; Fig. 5). Ravi do not explicitly disclose a digital to time conversion circuitry. In the same field of endeavor, Gross disclose a digital to time conversion circuitry (100, 350) (paras. [0022]-[0032], [0041]-[0042]; Figs. 1, 3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a digital to time conversion circuitry in order to provide circuitry to implement the time/phase shifting using delay lines (Gross; ¶ [0022]).
Claims 2-7 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ravi et al, "A 2.4-GHz 20 40-MHz Channel WLAN Digital Out-phasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS", IEEE Journal of Solid State Circuits, IEEE, USA, vol. 47, no. 12, December 1, 2012, (2012-12-01), pages 3184-3196, XP011485416, ISSN: 0018-9200, DOI: 10.1109/JSSC.2012.2216671) in view of Gross et al (US 2022/0,338,148) further in view of Palaskas et al (US 2019/0,214,944; hereinafter Palaskas).
Regarding claim 2, Ravi and Gross disclose the transmitter of claim 1, wherein the digital to time conversion circuitry comprises: an input for an external oscillator signal (signal from external LO); a first signal modulation circuit (upper phase modulator) configured to modulate the frequency of the local oscillator signal based on a first control signal (θ + φ); and a second signal modulation circuit (lower phase modulator) configured to modulate the frequency of the local oscillator signal based on a second control signal (φ - θ) (Ravi, pg. 3, col 2, lines 33-43; Fig. 5). Ravi and Gross do not disclose a multi-modulus divider configured generate a local oscillator signal having a frequency of a fraction of the frequency of the external oscillator signal, the fraction corresponding to an integer number. In the same field of endeavor, Palaskas disclose a multi modulus divider (340) configured generate a local oscillator signal having a frequency of a fraction of the frequency of the external oscillator signal (LO), the fraction corresponding to an integer number (Figs. 3-5; paras. [0029]-[0035]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do so in order to perform coarse modulation on periods of the LO signal to generate edge signals I and Q (Palaskas; ¶ [0030]).
Regarding claim 3, Ravi, Gross, and Palaskas disclose the transmitter of claim 2, further comprising delay circuitry (delay cells 721, 723, 725, 727) configured to delay the local oscillator signal by a number of cycles of the external oscillator signal (Ravi; pg. 7, Fig. 16; Palaskas;
¶ [0041], Fig. 7).
Regarding claim 4, Ravi, Gross, and Palaskas disclose the transmitter of claim 3, further comprising a phase delay circuit configured to delay the second control signal relative to the first control signal by the number of cycles of the external oscillator (Ravi, pg. 4, lines 1-3; Gross, paras. [0025], [0031]-[0032]).
Regarding claim 5, Ravi, Gross, and Palaskas disclose the transmitter of claim 3, wherein the number of cycles corresponds to an integer multiple of the integer number (Gross; paras. [0043]-[0045]).
Regarding claim 6, Ravi, Gross, and Palaskas disclose the transmitter of claim 1, further comprising an amplitude delay circuit configured to delay a second amplitude control word for the second amplifier relative to a first amplitude control word for the first amplifier by a number of cycles of the external oscillator (Ravi, pg. 9, col 1, lines 9-23; Gross; paras. [0030]-[0031]).
Regarding claim 7, Ravi, Gross, and Palaskas disclose the transmitter of claim 6, wherein the number of cycles corresponds to an integer multiple of the integer number (Gross; paras. [0043]-[0045]).
Regarding claim 12, Ravi and Palaskas disclose the method of claim 11, wherein the method further comprising: delaying the second control signal by a number of cycles of an external oscillator as compared to the first control signal (Ravi, pg. 4, lines 1-3). Ravi and Palaskas do not explicitly disclose delaying the second control signal relative to the first control signal by the number of cycles of the external oscillator. In the same field of endeavor, Gross disclose delaying the second control signal relative to the first control signal by the number of cycles of the external oscillator (paras. [0025], [0031]-[0032]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do so in order to offset the first control signal from the second control signal to delay the second modulated local oscillator signal based on the amount of oscillator cycles.
Regarding claim 13, Ravi, Gross, and Palaskas disclose the method of claim 12, wherein the number of cycles corresponds to an integer multiple of the integer number (Gross; paras. [0043]-[0045]).
Regarding claim 14, Ravi, Gross, and Palaskas disclose the method of claim 10, further comprising delaying a second amplitude control word for a second amplifier by a number of cycles of the external oscillator as compared to a first amplitude control word for a first amplifier (Ravi, pg. 9, col 1, lines 9-23; Gross; paras. [0030]-[0031]).
7. Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Ashoke Ravi et al, "A 2.4-GHz 20 40-MHz Channel WLAN Digital Out-phasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS", IEEE Journal of Solid State Circuits, IEEE, USA, vol. 47, no. 12, December 1, 2012, (2012-12-01), pages 3184-3196, XP011485416, ISSN: 0018-9200, DOI: 10.1109/JSSC.2012.2216671) in view of Gross et al (US 2022/0,338,148) in view of Palaskas et al (US 2019/0,214,944) further in view of Vergnes et al (US 5,977,805; hereinafter Vergnes).
Regarding claim 8, Ravi, Gross, and Palaskas disclose the transmitter of claim 3, wherein they do not disclose the delay circuitry comprises multiple shift registers connected in series, an input of the first shift register of the series being connected to the local oscillator signal, an output of the shift registers being connected to a multiplexer, wherein the shift registers are triggered by the external oscillator signal. In the same field of endeavor, Vergnes disclose a delay circuitry comprises multiple shift registers (151, 153) connected in series, an input of the first shift register of the series being connected to the local oscillator signal (143), an output of the shift registers (151, 153) being connected to a multiplexer (133), wherein the shift registers are triggered by an external oscillator signal (137) (Figs. 1, 7, 8; col 7, line 38 – col 8, line 27). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do so in order to use shift registers to divide the clock cycle of the local oscillator into delay units and to generate an output signal corresponding to the local oscillator frequency with a selected phase delay (col 9, lines 13-16, col 9, lines 62-65).
Regarding claim 9, Ravi, Gross, and Palaskas disclose the transmitter of claim 3, wherein they do not disclose the phase delay circuit comprises multiple shift registers connected in series, an input of the first shift register being configured to receive the second control signal, an output of the shift registers being connected to a multiplexer, wherein the shift registers are triggered by the external oscillator signal. In the same field of endeavor, Vergnes disclose a phase delay circuit comprises multiple shift registers (151, 153) connected in series, an input of the first shift register (153) being configured to receive a second control signal, an output of the shift registers (151, 153) being connected to a multiplexer (133), wherein the shift registers are triggered by an external oscillator signal (137). (Figs. 1, 7, 8; col 7, line 38 – col 8, line 27). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do so in order to have use shift registers to divide the clock cycle of the local oscillator into delay units and to generate an output signal corresponding to the local oscillator frequency with a selected phase delay (col 9, lines 13-16, col 9, lines 62-65).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ashoke Ravi et al, "A 2.4-GHz 20 40-MHz Channel WLAN Digital Out-phasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS", IEEE Journal of Solid State Circuits, IEEE, USA, vol. 47, no. 12, December 1, 2012, (2012-12-01), pages 3184-3196, XP011485416, ISSN: 0018-9200, DOI: 10.1109/JSSC.2012.2216671) in view of Palaskas et al (US 2019/0,214,944; hereinafter Palaskas).
Regarding claim 11, Ravi disclose the method of claim 10, further comprising modulating the frequency of the local oscillator signal based on a first control (θ + φ); and modulating the frequency of the local oscillator signal based on a second control signal (φ - θ) (Ravi, pg. 3, col 2, lines 33-43; Fig. 5). Ravi do not disclose generating a local oscillator signal having a frequency of a fraction of the frequency of the external oscillator signal, the fraction corresponding to an integer number. In the same field of endeavor, Palaskas disclose generating (via 340) a local oscillator signal having a frequency of a fraction of the frequency of the external oscillator signal (LO), the fraction corresponding to an integer number (Figs. 3-5; paras. [0029]-[0035]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do so in order to perform coarse modulation on periods of the LO signal to generate edge signals I and Q (Palaskas; ¶ [0030]).
5. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over ASHOKE RAVI et al, "A 2.4-GHz 20 40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS", IEEE JOURNAL OF SOLID STATE CIRCUITS, IEEE, USA, Vol. 47, no. 12, December 1, 2012, (2012-12-01), pages 3184-3196, XP011485416, ISSN: 0018-9200, D(OI: 10.1109/JSSC.2012.2216671) in view of Ravi et al (US 2012/0,062,331; hereinafter Ravi2).
Regarding claim 15, Ravi discloses an inherent non-transitory computer readable storage medium having stored thereon a program code for, when the program code is executed by hardware, causing:
generating a first modulated local oscillator signal (s1(t)) and a second modulated local oscillator signal (s2(t)) such that the second modulated local oscillator signal (s2(t)) has a delay to the first modulated local oscillator signal (s1(t)) (the second modulated LO signal is dynamically delayed in the phase modulator that output signal s2(t); Fig. 5; pg. 3, col 1, line 4 – col 2, line 44); triggering a first amplifier (upper amplifier of PA module) by the first modulated local oscillator signal (s1(t)); triggering a second amplifier (lower amplifier of PA module) by the second modulated local oscillator signal (s2(t)) pg. 3, col 2, lines 33-36); and
combining the signal output from the first amplifier and the signal output from the second amplifier (the two outphasing signals from the upper amplifier and the lower amplifier are then combined in a combiner; Fig. 5; pg. 3, col 2, lines 36-37). Ravi do not explicitly disclose a non-transitory computer readable storage medium having stored thereon a program code for, when the program code is executed by hardware causing: generating a first and second modulated local oscillator signal, triggering a first and second amplifier, and combining the signal output of the first and second amplifiers. In the same field of endeavor, Ravi2 disclose a non-transitory computer readable storage medium having stored thereon a program code for, when the program code is executed by hardware causing generating a first and second modulated local oscillator signal, triggering a first and second amplifier, and combining the signal output of the first and second amplifiers (paras. [0053]-[0055], [0044]-[0045]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do so in order to provide program instructions stored in a computer memory to be executed by the computer processor to perform the method steps as is notoriously old and well known in the art.
Conclusion
4. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
- Xu et al (US 2019/0,238,146), disclose a method for processing phase modulated input signal in wideband polar receiver architecture which involves operating injection locked oscillator to generate oscillator output signal and measuring phase of an oscillator output signal
- Staszewski et al (US 2008/0,055,008) discloses a local oscillator signal generating apparatus for a wireless device comprising a state machine programmable delay circuit that receives the output of an XOR circuit into which delayed and divided synthesized reference signals are input
- Otis et al (US 2013/0,058,384) discloses a transceiver which uses a frequency modulated reference clock signal to injection lock a local oscillator to provide an oscillation signal set each having an oscillation frequency that is equal to the first reference frequency, the oscillation signal set is combined into an output signal having an output frequency
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LANA N LE whose telephone number is (571) 272-7891. The examiner can normally be reached M-F 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wesley Kim can be reached at (571) 272-7867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LANA N LE/Primary Examiner, Art Unit 2648
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