DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Japan on 19 September 2023. It is noted, however, that applicant has not filed a certified copy of the JP2023-150693 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-10 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 of copending Application No. 18809799 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of App. ‘799 fall substantially within the metes and bounds of the claim limitations of the instant application.
Regarding claim 1, App. ‘799 claims (all limitations present in claim 1) a planar antenna comprising: an antenna array in which a plurality of patch antennas are disposed in a two-dimensional array; a substrate on which a phase shifter layer including a phase shifter associated with each of the plurality of patch antennas and wiring used for controlling the phase shifter is formed; a signal line through which a communication signal propagates; and a ground layer disposed between the phase shifter layer and the signal line, and having a slot formed at least between the signal line and the phase shifter.
The rest of the claims are either present in the subsequent dependent claims of the copending application or are obvious variants.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Marumoto et al. (U.S. Patent No. 6556168), hereinafter known as Marumoto.
Regarding claim 1, Marumoto discloses (Figs. 1-4, 15A-15B) a planar antenna (1) comprising: an antenna array (15) in which a plurality of patch antennas are disposed in a two-dimensional array (see Fig. 2); a substrate (36) on which a phase shifter layer (35) including a phase shifter (17) associated with each of the plurality of patch antennas and wiring used for controlling the phase shifter is formed (col. 16, lines 56-62); a signal line (23) through which a communication signal propagates (col. 5, lines 30-32); and a ground layer (layer including 22, col. 5, lines 44-46) disposed between the phase shifter layer and the signal line (see Fig. 2), and having a slot (22) formed at least between the signal line and the phase shifter (see Fig. 2).
Regarding claim 2, Marumoto further discloses (Figs. 1-4, 15A-15B) wherein the ground layer has a phase shifter slot below the phase shifter, and the signal line and the phase shifter are connected by electromagnetic coupling via the phase shifter slot (col. 6, lines 20-30).
Regarding claim 3, Marumoto further discloses (Figs. 1-4, 15A-15B) wherein the signal line includes a first signal line extending from a signal source to below or above a first end of the phase shifter and a second signal line extending from below or above a second end of the phase shifter to below the patch antenna, and wherein the first signal line is connected to the first end of the phase shifter by electromagnetic coupling, and the second signal line is connected to the second end of the phase shifter by electromagnetic coupling (see Fig. 15A, two signal lines coupling to two slots).
Regarding claim 4, Marumoto further discloses (Figs. 1-4, 15A-15B) wherein the first signal line is disposed while avoiding a lower region of the patch antenna in plan view (see Fig. 15B).
Regarding claim 5, Marumoto further discloses (Figs. 1-4, 15A-15B)wherein the ground layer has a patch slot (21) below the patch antenna, and the signal line and the patch antenna are connected via the patch slot (see Fig. 15B).
Regarding claim 6, Marumoto further discloses (Figs. 1-4, 15A-15B) wherein the signal line and the patch antenna are connected by electromagnetic coupling via the patch slot (see Fig. 15B).
Regarding claim 7, Marumoto further discloses (Figs. 1-4, 15A-15B) wherein the signal line and the patch antenna are connected by a power supply line via the patch slot (see alternate embodiment in Fig. 18B).
Regarding claim 8, Marumoto further discloses (Figs. 1-4, 15A-15B) wherein the ground layer is divided into a first ground layer having the patch slot and a second ground layer having the phase shifter slot, and the signal line is disposed between the first ground layer and the second ground layer (see Fig. 2, multiple ground layers with slots shown).
Regarding claim 9, Marumoto further discloses (Figs. 1-4, 15A-15B) a signal source (13) connected to the signal line included in the planar antenna (see Fig. 1); a matrix circuit (14) in which a plurality of thin film transistors connected to wiring included in the planar antenna are disposed in a two-dimensional array (see Fig. 1, col. 11, lines 8-11); a drive circuit (12X) that drives the thin film transistor included in the matrix circuit; and a control circuit (11) that drives the drive circuit in accordance with a control signal (see Fig. 1).
Regarding claim 10, Marumoto further discloses (Figs. 1-4, 15A-15B) wherein the control circuit causes the plurality of patch antennas included in the planar antenna to transmit a radio wave having directivity from the antenna array configured by the plurality of patch antennas (col. 4, lines 51-53).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Otsubo et al. (U.S. Patent Application No. 20200168746) teaches an antenna.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL MUNOZ whose telephone number is (571)270-1957. The examiner can normally be reached M-F 9 a.m. - 5 p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL MUNOZ/ Primary Examiner, Art Unit 2896