Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The Office has cited particular columns, line numbers, paragraph numbers, references, or figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Claim Objections
Claim 14 is objected to because of the following informalities: in line 17, “electrically connected a gate terminal” appears to be “electrically connected to a gate terminal”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stoerk et al. (US 2010/0277220 A1, hereinafter referred to as Stoerk).
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Regarding claim 1, Stoerk discloses a semiconductor integrated circuit (See Fig. 3 and annotated Fig. 5 above), comprising:
an input pin (210);
a switch (“Switch” Q6, see annotated Fig. 5 above) having a drain terminal (“D”) electrically connected to the input pin (210), and configured to be in an ON mode or an OFF mode (when EN is high, Switch Q6 is turned on, para 0028; and when EN is low, Switch Q6 is turned off, para 0027), responsive to a state of the input pin (when EN is high and input pin 210 is ON, source “S” of Switch Q6 is ON state; and when EN is high and input pin 210 is OFF, source “S” of “Switch” Q6 is OFF state, para 0028);
a first logic block (“1st Logic”, see annotated Fig. 5 above) electrically connected to a gate terminal (“G”) of the switch and a source terminal (“S”) of the switch;
a second logic block (“2nd Logic”, see annotated Fig. 5 above) electrically connected to the gate terminal (“G”) of the switch; and
a first node (“NODE1”) electrically connected to the first logic block, the second logic block, and the gate terminal of the switch.
Regarding claim 6, Stoerk discloses the semiconductor integrated circuit of claim 1, further comprising: a voltage source (VP); and a ground (VN), wherein the input pin (210) is free of having an electrical connection with the voltage source and the ground when the state of the input pin is a floating state (when EN is low, Q6 is turned off, para 0027).
Regarding claim 7, Stoerk discloses a semiconductor integrated circuit (See Fig. 3 and annotated Fig. 5 above), comprising:
an input pin (210);
a switch (“Switch” Q6, see annotated Fig. 5 above) including an N-type transistor (Q6) having a drain terminal (“D”) electrically connected to the input pin, said switch configured to be in an ON mode or an OFF mode (when EN is high, Switch Q6 is turned on, para 0028; and when EN is low, Switch Q6 is turned off, para 0027) in response to a state of the input pin (when EN is high and input pin 210 is ON, source “S” of Switch Q6 is ON state; and when EN is high and input pin 210 is OFF, source “S” of “Switch” Q6 is OFF state, para 0028);
a first logic block (“1st Logic”, see annotated Fig. 5 above) electrically connected to the switch, said first logic block including an N-type transistor logic block (see N-type transistors Q7, Q8), which is electrically connected to a ground voltage (VN), configured to generate a sink current (inherent for Q7 and Q8 connected to VN), and comprises:
a first transistor block (Q7); and
a pull-down current generation block (Q8) electrically connected (via gates and VN) to the first transistor block (Q7), and a gate terminal (“G”) and a source terminal (“S” via Q7 and Q9, Figs. 3, 5) of the N-type transistor (Q6);
a second logic block (“2nd Logic”, see annotated Fig. 5 above) electrically connected to the gate terminal (“G”) of the N-type transistor (Q6); and
a first node (“NODE1”) electrically connected to the first logic block, the second logic block, and the switch.
Allowable Subject Matter
Claims 2-5 and 8-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 14-20 are allowed.
The best prior art of record, Stoerk et al., teaches a semiconductor integrated circuit (Fig. 6) comprising: an input pin (210); a switch (Q16), wherein the switch is electrically connected to the input pin (210); a first logic block (Q13, Q14, R3, R4, Q15), wherein the first logic block is electrically connected to the switch; a second logic block (Q10, Q11, Q12), wherein the second logic block is electrically connected the switch; and a first node (gate of Q16) that is electrically connected to the first logic block, the second logic block, and the switch, wherein the switch comprises a P-type transistor (Q16), wherein the first logic block comprises a P-type transistor logic block (Q13, Q14), wherein the P-type transistor logic block comprises a current mirror block (Q14). However, one of ordinary skill in the art would not have been motivated to include: wherein the P-type transistor logic block comprises a pull-up current generation block, wherein the pull-up current generation block is electrically connected a gate terminal of the P-type transistor, and wherein the P-type transistor logic block is configured to generate a pull-up current, as set forth in the claim 14. The claims dependent on the above-discussed independent claim are allowable also because of their dependency on patentable independent claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tomioka et al. (US 2012/0062312 A1) discloses constant current circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL D CHANG whose telephone number is (571)272-1801. The examiner can normally be reached M-F 8-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 5712728048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL D CHANG/ Primary Examiner, Art Unit 2844