Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application has been examined. Claims 1-20 are pending.
The Group and/or Art Unit location of your application in the PTO has changed. To aid in correlating any papers for this application, all further correspondence regarding this application should be directed to Group Art Unit 2175.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claims 1-4 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claim 1 in Patent No. 12,111,780. Although the conflicting claims are not identical, they are not patentably distinct from each other because claim 1 of the US Patent No. 12,111,780 are similar in scope to claims 1-4 of the present application with only obvious wording variations.
6. Claims 5-7 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 3-5 in Patent No. 12,111,780 respectively. Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 3-5 of the US Patent No. 12,111,780 are similar in scope to claims 5-7 of the present application with only obvious wording variations.
7. Claim 9 is rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 8 and 13 in Patent No. 12,111,780. Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 8 and 13 of the US Patent No. 12,111,780 are similar in scope to claim 9 of the present application with only obvious wording variations.
8. Claims 10-15 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 9,12,10,11,14, 8 in Patent No. 12,111,780 respectively. Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 9, 12, 10, 11, 14, 8 of the US Patent No. 12,111,780 are similar in scope to claims 10-15 of the present application with only obvious wording variations.
9. Claims 16, 18, 20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 15, 17, 15 in Patent No. 12,111,780 respectively. Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 15, 17, 15 of the US Patent No. 12,111,780 are similar in scope to claims 16, 18, 20 of the present application with only obvious wording variations.
Present Application
Pat No. 12,111,780
1.A system comprising: a memory; a
first interface; and
a processing resource communicably coupled to the first interface and to the memory, the processing resource including:
a buffer; and a first controller configured to transmit a set of data from the buffer with associated trace information for the set of data to the memory;
a second interface; and a second controller configured to transmit the set of data with the associated trace information from the memory to the second interface.
2. The system of claim 1, wherein the first controller is further configured to transmit set of data without trace information from the buffer to the first interface.
3. The system of claim 2, wherein the first controller is configured to use different channels to transmit the set of data with the associated trace information and to transmit the set of data without trace information.
4. The system of claim 1, wherein each of the first and second controllers includes a direct memory access (DMA) controller.
5. The system of claim 1, wherein the second interface includes at least one of a camera serial interface and a peripheral component interconnect express interface.
6. The system of claim 1, further comprising an event bus communicably coupled to the processing resource and to the second controller, wherein the second controller is configured to transmit the set of data with the associated trace information from the memory to the second interface in response to a first signal received over the event bus indicating that the set of data from the buffer with the associated trace information has been transmitted to the memory.
7. The system of claim 6, wherein the processing resource further includes a scheduler, and wherein the scheduler is configured to: receive a second signal over the event bus indicating that transmission, by the second controller, of the set of data with the associated trace information from the memory to the second interface is complete; and cause the set of data to be removed from the buffer in response to receiving the second signal.
8. The system of claim 1, wherein the buffer is a line buffer, and the set of data is one or more lines of data.
9. A system comprising: a plurality of processing resources, each including a buffer 402, a scheduler 404, and a controller 408; an event bus 406; a system bus 414;
a memory 416 coupled to each of the plurality of processing resources via the system bus;
a first interface 410 coupled to the controller 408 of each of the plurality of processing resources;
a direct memory access (DMA) controller 418 coupled to the event bus 406 ; and
a second interface 420 coupled to the DMA controller.
Read on claim 1
10. The system of claim 9, wherein: the controller 408 of each of the plurality of processing resources is configured to transmit a set of data from the corresponding buffer to the first interface 410 and to transmit the set of data with associated trace information to the memory 416, and the DMA controller 418 is configured to transmit the set of data with the associated trace information from the memory to the second interface 420.
11. The system of claim 10, wherein the DMA controller is configured to transmit the set of data with the associated trace information from the memory to the second interface in response to receiving a signal via the event bus.
12. The system of claim 9, wherein the second interface includes at least one of a camera serial interface and a peripheral component interconnect express interface.
13. The system of claim 9, wherein the second interface is configured to couple the DMA controller to an external memory.
14. The system of claim 9, wherein a first processing resource of the plurality of processing resources is configured to modify a data processing rate of the first processing resource based on a signal received via the event bus from a second processing resource of the plurality of processing resources.
15. The system of claim 9, wherein each of the plurality of processing resources includes a hardware accelerator.
16. A method comprising: transmitting, by a first direct memory access (DMA) controller, data from a buffer of a processing resource to a first interface, wherein the data is comprised of elements; transmitting, by the first DMA controller, the elements of the data, each with associated trace information, to a memory;
transmitting, by the first DMA controller, a first signal to a second DMA controller over an event bus, wherein the first signal indicates completion of the transmission of the elements of the data, each with the associated trace information, to the memory;
transmitting, in response to the first signal, by the second DMA controller, the elements of the data, each with the associated trace information, to a second interface; and
transmitting, by the second DMA controller, a second signal to a scheduler for the buffer of the processing resource, wherein the second signal indicates completion of the transmission of the elements of the data, each with the associated trace information, to the second interface.
17. The method of claim 16, wherein: each of the first and second signals is transmitted over an event bus; the first DMA controller transmits the data from the buffer of the processing resource to the first interface over a system bus; the first DMA controller transmits the elements of the data, each with associated trace information, to the memory over the system bus; and the second DMA controller transmits the elements of the data, each with the associated trace information, to the second interface over the system bus.
18. The method of claim 16, wherein the first DMA controller: transmits the data from the buffer of the processing resource to the first interface over a first channel of the system bus; and transmits the elements of the data, each with associated trace information, to the memory over a second channel of the system bus.
19. The method of claim 16, wherein each element of the elements of the data is comprised of one or more lines of data.
20. The method of claim 16, wherein the transmitting, by the first DMA controller, of the data from the buffer of the processing resource to the first interface, and the transmitting, by the first DMA controller, the elements of the data, each with associated trace information, to the memory are performed in response to a signal received by the buffer from a scheduler of the processing resource.
1. A system
a first interface;
a the first processing resource comprising:
Claim 1
Claim 1
Claim 1
3. The system-on-chip of claim 1, wherein the second interface comprises at least one selected from a group consisting of CSI2 TX interface, a PCIE interface and Display.
4. The system-on-chip of claim 1, further comprising an event bus communicably coupled to the first processing resource and the second DMA controller, wherein the second DMA controller is configured to transmit the data with the associated trace information from the first memory device to the second interface in accordance with a first signal received over the event bus indicating the data from the data buffer with the associated trace information has been transmitted to the first memory device.
5. The system-on-chip of claim 4, wherein the first processing resource further comprises a scheduler, and wherein the scheduler is configured to: receive a second signal from the event bus indicating that the transmission by the second DMA controller is complete for a particular data set; receive a third signal from the event bus indicating that the transmission by the first DMA controller is complete for the particular data set; and in accordance with receiving the second signal and the third signal, cause the particular data set to be removed from the data buffer.
8. A system, comprising: a first hardware accelerator (HWA) comprising: a first buffer; a first scheduler communicably coupled to the first buffer; and a first direct memory access (DMA) controller 408; a system data bus; an event bus;
a first memory device 416 coupled to the first HWA via the system data bus;
a second interface 410 coupled to the first HWA [via first DMA controller 408]
a second DMA controller 418 coupled to the first HWA via the event bus;
a first interface 420 coupled to the second DMA controller 418 via the system data bus.
13. The system of claim 8, wherein the system further comprises: a second HWA comprising: a second buffer; a second scheduler; and a third DMA controller, wherein the second DMA controller is communicably coupled to the second HWA over the event bus and further configured to transmit data from the second buffer of the second HWA to the first memory device
9. The system of claim 8, wherein the first DMA controller 408 is configured to transmit data from the first buffer to the second interface 410 and to the first memory device 416, and wherein the second DMA controller 418 is configured to transmit data from the first memory device 416 to the first interface 420.
12. The system of claim 9, wherein the second DMA controller is configured to transmit a first data set from the first memory device to the first interface in accordance with receiving a signal via the event bus indicating the first data set is transmitted from the first buffer to the first memory device via the first DMA controller.
10. The system of claim 8, wherein the first interface comprises at least one selected from a group consisting of a CSI2 TX interface, PCIE interface and/or Display interface.
11. The system of claim 8, wherein the second interface comprises external DRAM memory.
14. The system of claim 13, wherein the first HWA is configured to modify a processing rate based on a signal received via the event bus from the second HWA.
Clam 8
15. A method, comprising: transmitting, by a first direct memory access (DMA) controller, a first data set from a buffer of a processing resource to a first interface and a second data set to a first memory device over a system data bus, wherein the second data set comprises the first data set and trace data for the first data set;
transmitting, by the first DMA controller, a first signal to a second DMA controller over an event bus, wherein the first signal indicates completion of the transmission of the first data set to the first interface;
transmitting, by the first DMA controller, a second signal to a scheduler for the buffer over the event bus, wherein the second signal indicates completion of the transmission of the second data set to the first memory device; and
in response to the second signal:
transmitting, by the second DMA, the second data set from the first memory device to a second interface over the system data bus; and
transmitting, by the second DMA, a third signal to the scheduler for the buffer over the event bus, wherein the third signal indicates completion of the transmission of the second data set to the second interface.
17. The method of claim 15, wherein the first DMA controller transmits the first data set over a first channel of the system data bus, and the first DMA controller transmits the second data set over a second channel of the system data bus.
Claim 15
In re Karlson, 136 USPQ 189 (ccPA 1963).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
10. Claims 1-6, 8-13, 15-19 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Lysaght et al. (US No. 10,691,856).
In regard to claims 1, 9, 13, 16, Lysaght et al. disclose a method, a system comprising: an event bus; a system bus; a memory (item 225 of figure 5C); a first interface (item 590 of figure 5C); and a processing resource (item 570 of figure 5C) communicably coupled to the first interface and to the memory, the processing resource including: a buffer (item 580 of figure 5C); and a first controller (item 582 of figure 5C) configured to transmit a set of data from the buffer with associated trace information for the set of data to the memory (as shown in Fig. 5C, which is reproduced below for ease of reference and convenience, Lysaght discloses trace buffer 572 is coupled to DMA circuit 582. DMA circuit 582 is capable of interacting with a memory controller 590. In one or more embodiments, DMA circuit 582 is implemented using programmable circuitry of IC 200. In one or more other embodiments, DMA circuit 582 is hardwired in IC 200. DMA circuit 582 is capable of reading data, e.g., trace data, from FIFO memory 580 and writing the trace data to memory 225 via memory controller 590. Memory controller 590 may be located on-chip with RCC 210 or off-chip for reading and/or writing to memory 225. DMA circuit 582 reads the sampled signal(s) from FIFO memory 580 and writes the sampled signals to memory 225 as trace data. Once armed and operating, trigger circuit 578 is capable of storing samples of the signal or signals within FIFO memory 580. FIFO memory 580 is capable of performing write mismatch resolution. See col. 26, lines 41-50; col. 27, line 52 through col 28, line 3);
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a second interface (item 590 of figure 5C); and a second controller configured to transmit the set of data with the associated trace information from the memory to the second interface (in Lysaght, processor 205 is capable of controlling operation of DMA circuit 582. Processor 205, for example, is capable of instructing DMA circuit 582 to begin writing data to memory 225 and/or stop writing data to memory 225. Further, processor 205 is capable of specifying the particular addresses of memory 225 to which trace data is to be written. See col. 28, lines 4-17).
In regard to claim 2, Lysaght et al. disclose wherein the first controller is further configured to transmit set of data without trace information from the buffer to the first interface (in Lysaght, switch 574, which may be implemented as one or more multiplexers, can be controlled, during operation from processor 205 to determine or select which of the signals are to be passed to trigger circuit 578. In this manner, an application executed by processor 205 is capable of choosing which of the signals are monitored by trace buffer 572 and under what conditions (e.g., at runtime) such signals are to be monitored by providing new and/or updated parameterization data. In particular embodiments, processor 205 is capable of instructing switch 574 as to which signals to pass at runtime, e.g., in real-time, to dynamically change the particular signals that are probed or evaluated at any given time. See col. 27, lines 16-52).
In regard to claim 3, Lysaght et al. disclose wherein the first controller is configured to use different channels to transmit the set of data with the associated trace information and to transmit the set of data without trace information (in Lysaght, switch 574, which may be implemented as one or more multiplexers, can be controlled, during operation from processor 205 to determine or select which of the signals are to be passed to trigger circuit 578. In this manner, an application executed by processor 205 is capable of choosing which of the signals are monitored by trace buffer 572 and under what conditions (e.g., at runtime) such signals are to be monitored by providing new and/or updated parameterization data. In particular embodiments, processor 205 is capable of instructing switch 574 as to which signals to pass at runtime, e.g., in real-time, to dynamically change the particular signals that are probed or evaluated at any given time. See col. 27, lines 16-52).
In regard to claim 4, Lysaght et al. disclose wherein each of the first and second controllers includes a direct memory access (DMA) controller (in Lysaght, signal capture circuitry 584, trace buffer 572, and direct memory access (DMA) circuit 582. Signal capture circuitry 584 represents signal connections where the input and output signals for each instance of circuit block 568 are routed or coupled to trace buffer 572. The DMA circuit 582 reads the trace data from FIFO memory 580 and writes the trace data to memory 225. DMA circuit 582 is capable of accessing a port on memory controller 590. Since other circuits are capable of accessing memory 225 via memory controller 590, there may be contention for writing data to memory 225. FIFO memory 580 alleviates backpressure in the event that sampled signals must be temporarily stored until DMA circuit 582 is able to continue writing data to memory 225. See col. 26, lines 15-50).
In regard to claims 5, 12, Lysaght et al. disclose wherein the second interface includes at least one of a camera serial interface and a peripheral component interconnect express interface (in Lysaght, interface circuitry 115 include, but are not limited to, a system bus and an input/output (I/O) bus. Interface circuitry 115 may be implemented using any of a variety of bus architectures. Examples of bus architectures may include, but are not limited to, Enhanced Industry Standard Architecture (EISA) bus, Accelerated Graphics Port (AGP), Video Electronics Standards Association (VESA) local bus, Universal Serial Bus (USB), and Peripheral Component Interconnect Express (PCIe) bus. See col. 6, lines 4-17).
In regard to claims 6, 17, Lysaght et al. disclose further an event bus communicably coupled to the processing resource and to the second controller, wherein the second controller is configured to transmit the set of data with the associated trace information from the memory to the second interface in response to a first signal received over the event bus indicating that the set of data from the buffer with the associated trace information has been transmitted to the memory (in Lysaght, trigger circuit 578 is capable of evaluating received signals for particular conditions or trigger events. Selected ones of the signals may be stored in FIFO memory 580, e.g., in response to detecting a particular trigger event. See col. 26, lines 24-40).
In regard to claims 8, 19, even though Kincaid does not disclose wherein each element of the elements of the data is comprised of one or more lines of data. However it is merely one of several straightforward possibilities from which the skilled person in the art would have each element of the data comprised of one or more lines of data in order to reduce bus contention, in accordance with circumstances, without the exercise of inventive skill, in order to solve the problem posed.
In regard to claim 10, Lysaght et al. disclose wherein: the controller of each of the plurality of processing resources is configured to transmit a set of data from the corresponding buffer to the first interface and to transmit the set of data with associated trace information to the memory, and the DMA controller is configured to transmit the set of data with the associated trace information from the memory to the second interface (in Lysaght, trace buffer 572 is coupled to DMA circuit 582. DMA circuit 582 is capable of interacting with a memory controller 590. In one or more embodiments, DMA circuit 582 is implemented using programmable circuitry of IC 200. In one or more other embodiments, DMA circuit 582 is hardwired in IC 200. DMA circuit 582 is capable of reading data, e.g., trace data, from FIFO memory 580 and writing the trace data to memory 225 via memory controller 590. Memory controller 590 may be located on-chip with RCC 210 or off-chip for reading and/or writing to memory 225. DMA circuit 582 reads the sampled signal(s) from FIFO memory 580 and writes the sampled signals to memory 225 as trace data. Once armed and operating, trigger circuit 578 is capable of storing samples of the signal or signals within FIFO memory 580. FIFO memory 580 is capable of performing write mismatch resolution. See col. 26, lines 41-50; col. 27, line 52 through col 28, line 3).
In regard to claim 11, Lysaght et al. disclose wherein the DMA controller is configured to transmit the set of data with the associated trace information from the memory to the second interface in response to receiving a signal via the event bus (in Lysaght, processor 205 is capable of controlling operation of DMA circuit 582. Processor 205, for example, is capable of instructing DMA circuit 582 to begin writing data to memory 225 and/or stop writing data to memory 225. Further, processor 205 is capable of specifying the particular addresses of memory 225 to which trace data is to be written. Trigger circuit 578 is capable of evaluating received signals for particular conditions or trigger events. Selected ones of the signals may be stored in FIFO memory 580, e.g., in response to detecting a particular trigger event. See col. 28, lines 4-17).
In regard to claim 15 wherein each of the plurality of processing resources includes a hardware accelerator (in Lysaght, host system 100 is capable of operating on circuit design 135 to generate a different version of circuit design 135 that utilizes one or more RCCs. Circuit design 135 may be specified using an HLL (e.g., C and/or C++), using a behavioral hardware description language (e.g., VHDL and/or Verilog), or using a graphical representation of the circuitry. See col. 6, lines 3-17).
In regard to claim 18, Lysaght et al. disclose wherein the first DMA controller: transmits the data from the buffer of the processing resource to the first interface over a first channel of the system bus; and transmits the elements of the data, each with associated trace information, to the memory over a second channel of the system bus (in Lysaght, switch 574, which may be implemented as one or more multiplexers, can be controlled, during operation from processor 205 to determine or select which of the signals are to be passed to trigger circuit 578. In this manner, an application executed by processor 205 is capable of choosing which of the signals are monitored by trace buffer 572 and under what conditions (e.g., at runtime) such signals are to be monitored by providing new and/or updated parameterization data. In particular embodiments, processor 205 is capable of instructing switch 574 as to which signals to pass at runtime, e.g., in real-time, to dynamically change the particular signals that are probed or evaluated at any given time. See col. 27, lines 16-52).
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Allowable Subject Matter
11. Claims 7, 14, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
12. The following is an Examiner's statement of reasons for the indication of allowable subject matter: Claims 7, 14, 20 are allowable over the prior art of record because the prior arts, cited in its entirety, or in combination, do not teach
wherein the processing resource further includes a scheduler, and wherein the scheduler is configured to: receive a second signal over the event bus indicating that transmission, by the second controller, of the set of data with the associated trace information from the memory to the second interface is complete; and cause the set of data to be removed from the buffer in response to receiving the second signal (claim 7);
wherein a first processing resource of the plurality of processing resources is configured to modify a data processing rate of the first processing resource based on a signal received via the event bus from a second processing resource of the plurality of processing resources (claim 14);
wherein the transmitting, by the first DMA controller, of the data from the buffer of the processing resource to the first interface, and the transmitting, by the first DMA controller, the elements of the data, each with associated trace information, to the memory are performed in response to a signal received by the buffer from a scheduler of the processing resource (claim 20).
Conclusion
13. All claims are rejected.
14. The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Rao et al. (US Pub No. 2017/0363711) disclose a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples.
Nandan et al. (US Pub No. 2021/0326276) disclose an apparatus, including a local memory, a first hardware accelerator (HWA), a second HWA, the second HWA and the first HWA connected in a flexible data pipeline, and a spare scheduler to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA and the second HWA through the local memory and a memory.
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
Communications via Internet e-mail regarding this application, other than those under 35 U.S.C. 132 or which otherwise require a signature, may be used by the applicant and should be addressed to [raymond.phan@uspto.gov].
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175