Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1, 8 and 16.
b. Claims 1-20 are pending on the application.
Drawings
2. The drawings were received on 08/29/2024. These drawings are review and accepted by examiner.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 08/29/2024. The information disclosed therein was considered.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park (Patent No.: US 9,646,658 B1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1, Park in Figures 1-6 are directly disclosed a memory device (a memory device 3, Fig. 3) comprising:
a memory cell array (a memory cell array 310, Fig. 3);
an input/output circuit (a data input/output circuit 350, Fig. 3) configured to receive data to be stored in the memory cell array (the memory cell array 310) based on a write clock signal (a gate signal IOST coupled to a sense amplifier circuit 130, Fig. 3) received from an external device during a write operation (the page buffer array 340 may store data in the memory cell accessed by the row address RADD input to the row decoder 320 and the column address CADD input to the column decoder 330 through the data input/output circuit 350, Fig. 3, column 31-46 and the page buffer array 340 such as the sense amplifier circuit 100 includes the write clock signa IOST, Figs. 1-3); and
a clock amplifier circuit (a sense amplifier enable circuit 150, 250, Figs. 1-2) configured to provide an internal clock signal (a clock signal IOSTB<0:1>, Figs. 1-2) to the input/output circuit (the data input/output circuit 350) by amplify the write clock signal (a gate signal IOST coupled to a sense amplifier circuit 130, Fig. 3) and include a folded cascode amplifier (a sense amplifier circuit 120, 220, Figs. 1-2) which amplifies the write clock signal (the gate signal IOST coupled to a sense amplifier circuit 130, Fig. 3), wherein the folded cascode amplifier (the sense amplifier circuit 120, 220) is configured to amplify the write clock signal (the gate signal IOST coupled to a sense amplifier circuit 130) according to a gain between an input unit (input circuit 112 and 111, Figs. 1-2) and an output unit (output OUT, OUTB, Figs. 1-2), and include a gain adjustment unit which is connected to the output unit and increases the gain between the input unit and the output unit based on the write clock signal (the gate signal IOST coupled to a sense amplifier circuit 130) (for example, the sense amplifier 120, 220 such as amplify the voltage level changes of amplification nodes AN1, AN2 and generate a pair of output signal OUT, OUTB into the memory device 3, see at least in Fig. 1-3, column 1, lines 31-33 and column 2, lines 45 to column 10, lines 19 and the related disclosures).
Allowable Subject Matter
7. Claims 2-7, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claim 2, the prior art fails to tech or suggest the claimed limitations, namely, the memory device, wherein the clock amplifier circuit comprises: the folded cascode amplifier configured to amplify the write clock signal and output a first amplified clock signal; a current mode logic configured to amplify the first amplified clock signal and output a second amplified clock signal; and a CML divider configured to divide the second amplified clock signal to output the internal clock signal.
With respected to dependent claims 3-7, the prior art fails to tech or suggest the claimed limitations, namely, the memory device, wherein the input unit comprises: a first P-type transistor configured to include a gate to which the write clock signal is applied, a source which is connected to a first current source and a drain which is connected to a first node; and a second P-type transistor configured to include a gate to which a complementary write clock signal is applied, a source which is connected to the first current source and a drain which is connected to a second node, wherein the output unit comprises: a first N-type transistor configured to include a gate which is connected to a third node, a drain which is connected to a first main resistor, and a source which is connected to the first node; and a second N-type transistor configured to include a gate which is connected to a fourth node, a drain which is connected to a second main resistor, and a source which is connected to the second node, wherein the drain of the first N-type transistor is configured to output a complementary amplified clock signal which is inverted and amplified from the write clock signal, and wherein the drain of the second N-type transistor is configured to output an amplified clock signal which is inverted and amplified from the complementary write clock signal.
8. Claims 8-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
There is no teaching or suggestion in the prior art to provide:
Per claim 8: there is no teaching, suggestion, or motivation for combination in the prior art to “a differential output unit configured to output a first differential amplified signal in response to the first differential current signal and output a second differential amplified signal in response to the second differential current signal; and a gain adjustment unit configured to determine a gain between the first differential input signal and the first differential amplified signal based on the second differential current signal, and determine a gain between the second differential input signal and the second differential amplified signal based on the first differential current signal” in a folded cascode amplifier circuit as claimed in the independent claim 8. Claims 9-15 are also allowed because of their dependency on claim 8; or
Per claim 16: there is no teaching, suggestion, or motivation for combination in the prior art to “a second differential amplification unit configured to receive a second differential input signal complementary to the first differential input signal and output a second differential amplified signal which is inverted and amplified from the second differential input signal; a first DC gain adjustment unit configured to increase a DC gain of the first differential amplification unit based on the second differential input signal; a second DC gain adjustment unit configured to increase a DC gain of the second differential amplification unit based on the first differential input signal; a first AC gain adjustment unit configured to increase an AC gain of the first differential amplification unit based on the first differential input signal; and a second AC gain adjustment unit configured to increase an AC gain of the second differential amplification unit based on the second differential input signal” in a folded cascode amplifier circuit as claimed in the independent claim 16. Claims 17-20 are also allowed because of their dependency on claim 16.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Oak et al (US. 10,566,035 B2) discloses sense amplifier and semiconductor memory apparatus using the sense amplifier.
Jones (US. 7,176,760 B2) discloses CMOS class AB folded cascode operational amplifier for high-speed application.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
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/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov