DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 22-31 and 33 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bruestle et al. 20180107456 herein Bruestle.
Per claim 22, Bruestle discloses: one or more virtual machines (VMs) configured to generate a reconfigurable architecture for performing a simulation, wherein each of the one or more VMs comprises an abstraction of a computer engine, (¶0022; A compiled ML application 212 may execute either directly on a server 106 or on a virtual machine 110. The server 106 and/or the virtual machine 110 may be provisioned by one or more ML frameworks and/or runtimes 214. A ML hardware acceleration unit 216 may be connected to a server 106 or may be standalone. As a resource of a server 106, a ML hardware acceleration unit may be disaggregated as well by hypervisor 108 thereby making its resources available to a virtual machine 110; ¶0031; a compiled application 212 which may then be deployed for execution in block 312. The target platform may be a virtual machine 210 or alternatively a docker container hosted on the cloud 204 and may be deployed via orchestration/developer operations software such as Chef ) and wherein the reconfigurable architecture comprises: one or more SI modules configured to automatically perform at least one of (i) multi- physics or multi-scale modeling, (ii) surrogate modeling and emulation, (iii) simulation- based inference, (iv) causal modeling and inference, or (v) agent-based modeling, (¶0032; The TILE language (Tensor Intermediate Language Engine) is a compact language for describing dense linear algebra operations such as convolution, matrix multiplication, or max pooling. TILE is also designed to allow machine code generation, i.e. compilation similar to many programming languages for efficient execution on highly parallel processor architectures such as Graphical Processing units (GPUs), traditional vector processors, systolic arrays, or purpose-built application specific integrated circuits (ASIC).) and one or more SI workflows configured to automatically determine a simulation framework of the one or more SI modules for performing the simulation; (¶0032; These dense linear algebra operations include the computations comprising machine learning workflows including deep neural networks. In addition, the TILE representation lends itself to simple automatic differentiation) and a compiler configured to compile software executed on the one or more VMs for performing the simulation, wherein the compiler is configured to or is capable of automatic differentiation (autodiff) and/or probabilistic programming (¶0015; TILE compiler 106 comprises a receiving software component 108, which receives a computer readable representation of one or more algorithms. One example of such a representation is the TILE intermediate code. The receiving software component 108 then stores the code in a computer readable memory, ¶0032; The TILE language (Tensor Intermediate Language Engine) is a compact language for describing dense linear algebra operations such as convolution, matrix multiplication, or max pooling. TILE is also designed to allow machine code generation, i.e. compilation similar to many programming languages for efficient execution on highly parallel processor architectures such as Graphical Processing units (GPUs), traditional vector processors, systolic arrays, or purpose-built application specific integrated circuits (ASIC). These dense linear algebra operations include the computations comprising machine learning workflows including deep neural networks. In addition, the TILE representation lends itself to simple automatic differentiation).
Per, claim 23 Bruestle discloses: wherein the one or more SI workflows comprises (i) inverse design, (ii) open-ended optimization, (iii) continual learning, (iv) causal inference and discovery, (v) simulator inversion, (vi) human machine inference or active science), (vii) uncertainty reasoning, (viii) counterfactual reasoning, (ix) digital twins, (x) multi-modal simulation, or (xi) physics-informed learning (fig.1 ¶0014; preprocessing tensor operations for optimal compilation according to the present disclosure. A machine learning (ML) acceleration hardware is usually employed by, or embedded in, a chosen targeted computing platform 102, which is to ultimately run a ML application. A compiling computing device (not shown) takes in intermediate code generated by TILE generator 104 and forwards it to TILE compiler 106).
Per, claim 24 Bruestle discloses: wherein performing the simulation comprises simulating at least one problem in physics, complexity, synthetic biology, chemistry, materials, medicine, systems biology, neurological or cognitive sciences, energy, manufacturing, transportation and infrastructure, agriculture, ecology, socioeconomics and markets, finance, geopolitics, defense, climate, earth systems, astrophysics, or cosmology(¶0032; The TILE language (Tensor Intermediate Language Engine) is a compact language for describing dense linear algebra operations such as convolution, matrix multiplication, or max pooling. TILE is also designed to allow machine code generation, i.e. compilation similar to many programming languages for efficient execution on highly parallel processor architectures such as Graphical Processing units (GPUs), traditional vector processors, systolic arrays, or purpose-built application specific integrated circuits (ASIC). These dense linear algebra operations include the computations comprising machine learning workflows including deep neural networks. In addition, the TILE representation lends itself to simple automatic differentiation).
Per, claim 25 Bruestle discloses: wherein the one or more VMs comprises autodiff capabilities (¶0032; The TILE language (Tensor Intermediate Language Engine) is a compact language for describing dense linear algebra operations such as convolution, matrix multiplication, or max pooling. TILE is also designed to allow machine code generation, i.e. compilation similar to many programming languages for efficient execution on highly parallel processor architectures such as Graphical Processing units (GPUs), traditional vector processors, systolic arrays, or purpose-built application specific integrated circuits (ASIC). These dense linear algebra operations include the computations comprising machine learning workflows including deep neural networks. In addition, the TILE representation lends itself to simple automatic differentiation).
Per claim 26, Bruestle discloses: wherein the autodiff capabilities comprise emitting gradient programs at intermediate representations (IR) and/or at the instruction set (fig. 1, ¶0014-15; A machine learning (ML) acceleration hardware is usually employed by, or embedded in, a chosen targeted computing platform 102, which is to ultimately run a ML application. A compiling computing device (not shown) takes in intermediate code generated by TILE generator 104 and forwards it to TILE compiler 106.[0015] TILE compiler 106 comprises a receiving software component 108, which receives a compumter readable representation of one or more algorithms. One example of such a representation is the TILE intermediate code. The receiving software component 108 then stores the code in a computer readable memory).
Per claim 27, Bruestle discloses: wherein the one or more VMs are parameterized (¶0013; preprocessing operations to optimize subsequent code generation during compilation. In particular, the techniques disclosed, relate to preprocessing linear algebra and/or tensor constructs represented in a computer readable representation, such as source code in a programming computer language or an intermediate language such as TILE, ¶0025; In the preprocessing pass, an original computer readable representation of a mathematical operations is transformed into a form that will either enable generation of code, or may optimize generation of code. Optimization of generation may be in the form of using less computational cycles than without the transformation, or in other optimizations.)
Per claim 28, Bruestle discloses: wherein the one or more VMs comprises one or more parameters to be optimized (¶0013; preprocessing operations to optimize subsequent code generation during compilation. In particular, the techniques disclosed, relate to preprocessing linear algebra and/or tensor constructs represented in a computer readable representation, such as source code in a programming computer language or an intermediate language such as TILE ¶0025; In the preprocessing pass, an original computer readable representation of a mathematical operations is transformed into a form that will either enable generation of code, or may optimize generation of code. Optimization of generation may be in the form of using less computational cycles than without the transformation, or in other optimizations.).
Per claim 29, Bruestle discloses: wherein the one or more parameters comprises a size of memory, number and/or width of registers, available instruction set, instruction encoding, implementation of firmware, input/output (I/O), or any combination thereof (¶0019, ¶0030, ¶0038).
Per claim 30, Bruestle discloses: wherein the compiler comprises a multi-level intermediate representation (MLIR) compiler or a low-level intermediate representation (LLVM IR) compiler (¶0019, ¶0030, ¶0038; Transforming the TILE representation to optimized platform-specific code such as OpenCL, CUDA, SPIR-V, or processor-specific machine code is challenging. TILE operations are compiled in two major stages. During the first stage, simplification, a number of mathematical transforms on the original operation are performed, resulting in a new version of the operation which meets certain criteria which simplify later analysis, but otherwise performs the same operation. Specifically, the original operation is “flattened” which removes the dimensionality of tensors, keeping only stride information. This simplified and flattened version of the operation is then passed to the second stage, code generation, during which it is further analyzed and turned into code for the platform in question. It is during the code generation stage when thread assignment, memory layout, tiling (for cache optimization) and other related steps are performed).
Per claim 31, Bruestle discloses: wherein the autodiff comprises converting a programming language into machine code processed on heterogeneous hardware (¶0019, ¶0032; The TILE language (Tensor Intermediate Language Engine) is a compact language for describing dense linear algebra operations such as convolution, matrix multiplication, or max pooling. TILE is also designed to allow machine code generation, i.e. compilation similar to many programming languages for efficient execution on highly parallel processor architectures such as Graphical Processing units (GPUs), traditional vector processors, systolic arrays, or purpose-built application specific integrated circuits (ASIC). These dense linear algebra operations include the computations comprising machine learning workflows including deep neural networks. In addition, the TILE representation lends itself to simple automatic differentiation).
Per claim 33, Bruestle discloses: wherein the one or more VMs run on a graphics processing unit (GPU), a central processing unit (CPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a non-volatile memory express (NVMe), a microcontroller, an artificial intelligence (AI)-accelerator, or any combination thereof (¶0032; The TILE language (Tensor Intermediate Language Engine) is a compact language for describing dense linear algebra operations such as convolution, matrix multiplication, or max pooling. TILE is also designed to allow machine code generation, i.e. compilation similar to many programming languages for efficient execution on highly parallel processor architectures such as Graphical Processing units (GPUs), traditional vector processors, systolic arrays, or purpose-built application specific integrated circuits (ASIC). These dense linear algebra operations include the computations comprising machine learning workflows including deep neural networks. In addition, the TILE representation lends itself to simple automatic differentiation).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Breustle in view of Cotton 20190066133 herein Cotton.
Per claim 32, Bruestle does not specifically disclose: wherein the compiler enables the use of probabilistic programming, domain specific languages, differentiable programming, or any combination thereof.
However, Cotton discloses: wherein the compiler enables the use of probabilistic programming, domain specific languages, differentiable programming, or any combination thereof (¶0268; differentiable function represented by a multilayer perceptron with parameters θ.sub.g. We also define a second multilayer perceptron D(x; θ.sub.d) that outputs a single scalar. D(x) represents the probability that x came from the data rather than p.sub.g).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Bruestle and Cotton’s differential programming to allow for the use of differentiable function in compiling VM’s (¶0268).
Claim(s) 34-41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Breustle in view of Kumar 20200250510 herein Kumar.
Per claim 34, Bruestle does not specifically disclose: wherein the AI-accelerator comprise Google-TPU®, Graphcore®, Cerebras®, SambaNova®, or a combination thereof.
However, Kumar discloses: wherein the AI-accelerator comprise Google-TPU®, Graphcore®, Cerebras®, SambaNova®, or a combination thereof (¶0127; an AI training model split across a full stack AI SW framework running on multiple VMs with multi processors and multiple GPUs with vGPUs/TPUs as accelerators. The AI training model shown in FIG. 19, requires extensive hardware such as PCI path to/from CPU where AI framework running and GPU and software thread overhead, data copy and duplication, data preparation and pre-processing, mapping and transfer overhead at every stage of full stack processing including between CPU and GPU/TPU at every iteration of a model training. In the AI system lane according to the present disclosure, the processing overhead shown in FIG. 19 does not include a software stack driven model processing engine and does not incur software and processor overhead along the processing path during the model training. ).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Bruestle and Kumar’s AI application enable real time and highspeed secure AI solution without external hardware resources (¶0049).
Per claim 35, Bruestle discloses: wherein about 1000 VMs run on a GPU (¶0127; an AI training model split across a full stack AI SW framework running on multiple VMs with multi processors and multiple GPUs with vGPUs/TPUs as accelerators; the examiner notes that the number is merely a design choice ).
Per claim 36, Bruestle discloses: wherein about 10,000 VMs run on a GPU (¶0127; an AI training model split across a full stack AI SW framework running on multiple VMs with multi processors and multiple GPUs with vGPUs/TPUs as accelerators; the examiner notes that the number is merely a design choice ).
Per claim 37, Bruestle discloses: wherein about 500 VMs run on a CPU (¶0127; an AI training model split across a full stack AI SW framework running on multiple VMs with multi processors and multiple GPUs with vGPUs/TPUs as accelerators; the examiner notes that the number is merely a design choice ).
Per claim 38, Bruestle discloses: wherein the system allows for machine programming across a stack (¶0127; AI training model split across a full stack AI SW framework running on multiple VMs with multi processors and multiple GPUs with vGPUs/TPUs as accelerators. The AI training model shown in FIG. 19, requires extensive hardware such as PCI path to/from CPU where AI framework running and GPU and software thread overhead, data copy and duplication, data preparation and pre-processing, mapping and transfer overhead at every stage of full stack processing including between CPU and GPU/TPU at every iteration of a model training.; the examiner notes that the number is merely a design choice ).
Per claim 39, Bruestle discloses: wherein the system further comprises a software stack, a hardware stack, or a hardware-software stack (¶0052; The AI system single lane framework provides direct AI solution model processing hardware that can take in the model and corresponding training/inference data directly into hardware without any full stack software overhead in the processing path. The integration of these blocks in a single hardware structure and used in computation of each layer in serial pipeline is believed not to found elsewhere. The fundamental hardware construct of the AI system lane according to the present disclosure comprises a series of AI processing elements operating on a real-time continuous basis at clock speed with constant latency. Unlike a CPU+GPU/tensor processing unit (TPU) accelerator combination implementation, the present AI system lane does not require back and forth multi pass between CPU and GPU/TPU for forward or backward propagation during inference/training. That is, the classic learning approach is to collect the data, then train it using dozens of GPU/CPUs in combination. The produced output is used in inference. Hence, typically there no continuous training and inference running in low latency. In contrast, the approach of the AI System of the present disclosure by using inference AI PLUs and backpropagation AI PLUs provides for continuous training and inference. It is not believed there is another architecture that could do this right know.; the examiner notes that the number is merely a design choice ).
Per claim 40, Bruestle discloses: wherein the software stack, the hardware stack, the hardware- software-stack, or any combination thereof, is differentiable (¶0052; The AI system single lane framework provides direct AI solution model processing hardware that can take in the model and corresponding training/inference data directly into hardware without any full stack software overhead in the processing path. The integration of these blocks in a single hardware structure and used in computation of each layer in serial pipeline is believed not to found elsewhere. The fundamental hardware construct of the AI system lane according to the present disclosure comprises a series of AI processing elements operating on a real-time continuous basis at clock speed with constant latency. Unlike a CPU+GPU/tensor processing unit (TPU) accelerator combination implementation, the present AI system lane does not require back and forth multi pass between CPU and GPU/TPU for forward or backward propagation during inference/training. That is, the classic learning approach is to collect the data, then train it using dozens of GPU/CPUs in combination. The produced output is used in inference. Hence, typically there no continuous training and inference running in low latency. In contrast, the approach of the AI System of the present disclosure by using inference AI PLUs and backpropagation AI PLUs provides for continuous training and inference. It is not believed there is another architecture that could do this right know.; the examiner notes that the number is merely a design choice ).
Per claim 41, Bruestle discloses: wherein the software stack, the hardware stack, the hardware- software stack, or any combination thereof, enables gradient-based learning and/or optimization (¶0052; The AI system single lane framework provides direct AI solution model processing hardware that can take in the model and corresponding training/inference data directly into hardware without any full stack software overhead in the processing path. The integration of these blocks in a single hardware structure and used in computation of each layer in serial pipeline is believed not to found elsewhere. The fundamental hardware construct of the AI system lane according to the present disclosure comprises a series of AI processing elements operating on a real-time continuous basis at clock speed with constant latency. Unlike a CPU+GPU/tensor processing unit (TPU) accelerator combination implementation, the present AI system lane does not require back and forth multi pass between CPU and GPU/TPU for forward or backward propagation during inference/training. That is, the classic learning approach is to collect the data, then train it using dozens of GPU/CPUs in combination. The produced output is used in inference. Hence, typically there no continuous training and inference running in low latency. In contrast, the approach of the AI System of the present disclosure by using inference AI PLUs and backpropagation AI PLUs provides for continuous training and inference. It is not believed there is another architecture that could do this right know.; the examiner notes that the number is merely a design choice ).
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
Prosecution Insights