Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1 and 9.
b. Claims 1-10 are pending on the application.
Drawings
2. The drawings were received on 11/08/2024. These drawings are review and accepted by examiner.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 03/10/2025. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 08/29/2024. The information disclosed therein was considered.
Specification
5. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. It is important that the abstract not exceed 150 words in length since the space provided for the abstract on the computer tape used by the printer is limited. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc.
The abstract of the disclosure is objected to because it uses the phrase “Disclosed is” in page 1, line 1, which is implied. Correction is required. See MPEP § 608.01(b).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1, 6 and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al (Pub. No.: US 2022/0357922 A1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1, Lee et al in Figures 1-14 are directly discloses a computing-in-memory device (a MAC computation circuit 100, Figures 1 and 3) comprising:
a memory cell array (a bit-cell array 11, Fig. 1) including a plurality of local arrays configured to generate a first output signal (Analog output 102) and a second output signal (Digital output 103) by performing a multiply-accumulate (MAC) operation on an input signal (input signal 101, Fig. 1) applied through a plurality of operation word lines and a stored weight (the bit-cell array 11 form an input line, and each column of the bit-cell array 111 form an output line, an input value of one bit cell may be a value of a voltage applied to the bit cell by the input signal 101 and a weight value of the bit cell array may be a resistance value of the bit cell, column 3, paragraph 0056);
a reference voltage generator (a reference voltage generator 320, Fig. 3) configured to generate a reference voltage by sharing charges of the first output signal (the analog output 102 and 301) with adjacent global bit lines (the reference voltage generator 320 determine second reference voltage based on at least a portion of reference voltage that set the first range among the primary reference voltage, column 4, paragraph 0062); and
an analog-to-digital converter (an ADC block 120, Fig. 1 and 300, Fig. 3) configured to compare the reference voltage with the second output signal (the digital output 103) and to convert the second output signal (the digital output 103) into a digital signal based on a result of the comparison (an ADC block 120 include a first ADC circuit 121 and a second ADC circuit 122 for determined an upper part 104 and lower part 105; respectively. For example, the ADC circuit 121 determine an upper part 104 (high order bits) of the digital output 103 corresponding to the analog output 102 based on the analog output 102. The second ADC circuit 122 determine a lower part 105 (low order bits) of the digital output 103 base on analog output 102 and the reference voltage, see at least in Figure 1, column 3, paragraph 0054 to column 4, paragraph 0058 and paragraph 0062 and the related disclosures).
Regarding dependent claim 6, Lee et al in Figures 1-14 are directly discloses a computing-in-memory device (a MAC computation circuit 100, Figures 1 and 3) wherein the reference voltage generator (the reference voltage generator 320) determines a first global bit line as a master bit line (the first ADC circuit 121 generate the output as the upper part 104 (the high order bits), and determines a second global bit line adjacent to the first global bit line as a slave bit line (the second ADC circuit 122 generate the output as the lower part 105 (the lower order bit), Figs. 1 and 3).
Regarding dependent claim 8, Lee et al in Figures 1-14 are directly discloses a computing-in-memory device (a MAC computation circuit 100, Figures 1 and 3) wherein the digital signal is a 5-bit signal (the digital output 103 is generate by the MAC computation circuit 100 that the processor may use the digital output 103 as a result of the MAC operation) with respect to the second output signal (the digital output 103).
Regarding claim 9, they encompass the same scope of invention as that of claims 1, 6 and 8 except they draft the invention in method format instead of apparatus format. Lee et al. teach all the necessary elements to perform the method of these claims. The aspects of the invention contained in claim 9, is therefore rejected in method format for the same reasons claims 1, 6 and 8, were rejected in apparatus format, as discussed above in the prior paragraphs of the office action.
Allowable Subject Matter
7. Claims 2-5, 7 and 10, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claims 2-5, the prior art fails to tech or suggest the claimed limitations, namely the computing-in-memory device, wherein the local array includes: a local cell including a plurality of first transistors storing the weight and a second transistor computing the input signal and configured to generate a result of the MAC operation with respect to the input signal using the plurality of first transistors and the second transistor; and a peripheral circuit located below the local cell and configured to transfer the result of the MAC operation to a global bit line pair, wherein the local cell generates: a least significant bit by multiplying the input signal by the weight so as to transfer to a local bit line bar, and a most significant bit by multiplying an inverted signal of the input signal by the weight so as to transfer to a cell strapping line and a common source line.
With respected to dependent claim 7, the prior art fails to tech or suggest the claimed limitations, namely the reference voltage generator generates the reference voltage having 16 different voltage levels by sharing charges of the master bit line and the slave bit line.
With respected to dependent claim 10, the prior art fails to tech or suggest the claimed limitations, namely the generating of the reference voltage includes determining a first global bit line as a master bit line, determining a second global bit line adjacent to the first global bit line as a slave bit line, and generating the reference voltage having 16 different voltage levels by sharing charges of the master bit line and the slave bit line.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin et al (US. 11,423,983 B2) discloses memory device and data weight state determining method for in memory computation.
Nam et al (US. 12,474,890 B2) discloses semiconductor memory apparatus and operation method thereof.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov