DETAILED ACTION
Claims 1 – 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 and 11 are objected to because of the following informalities:
Claims 1 and 11 recite the limitation “perform operation of a NN model” has typo error. It is supposed to be “performance operation of the NN model”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 1, claim 1 line 6 recites the limitation “a clock signal supply circuit configured to output one or more clock signals” render the claim indefinite because the claim recites a first and second clock signal. It should be “a clock signal supply circuit configured to output a plurality of clock signals”.
Claim 11 is rejected for the same reasons as set forth in claim 1.
All other dependent claims are rejected for their dependency.
Regarding claims 2,4,6,12,14,16, these claims recite “the original clock signal”. There is insufficient antecedent basis for this limitation in the claims. It should be “an original clock signal”.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-16 of U.S. Patent 12117866 B2. Although the conflicting claims are not identical, they are not patentably distinct from each other because the claims are directed to substantially the same subject matter involving controlling the clock phases for first and second clock signal, respectively based on a peak power of the system on chip (SoC).
Instant Application 18819437
US Patent 12117866 B2
1. A system-on-chip (SoC) comprising:
a first circuitry provided for a first neural processing unit (NPU) configured to perform operations of a neural network (NN) model;
a second circuitry provided for a second NPU configured to perform operations of a NN model; and
a clock signal supply circuit configured to output one or more clock signals, wherein each of the first NPU and the second NPU includes a plurality of processing elements (PEs),
wherein a first clock signal among the one or more clock signals, is supplied to the first NPU, and a second clock signal among the one or more clock signals, is supplied to the second NPU, wherein at least one of the first and second clock signals has a preset phase, and wherein the first NPU is configured to operate based on a first phase of the first clock signal, and
the second NPU is configured to operate based on a second phase of the second clock signal,
wherein a phase difference between the first and second clock signals is determined in consideration of a peak power of the SoC.
1. A system-on-chip (SoC) comprising: a semi-conductor substrate;
a first circuitry, disposed on the semi-conductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model;
a second circuitry, disposed on the semi-conductor substrate, provided for a second NPU configured to perform operations of an ANN model; and
a clock signal supply circuit, disposed on the semi-conductor substrate, configured to output one or more clock signals, wherein each of the first NPU and the second NPU includes a plurality of processing elements (PEs), and the plurality of PEs include an adder, a multiplier, and an accumulator, wherein a first clock signal among the one or more clock signals, is supplied to the first NPU, and a second clock signal among the one or more clock signals, is supplied to the second NPU, wherein at least one of the first and second clock signals has a preset phase based on a phase of an original clock signal, and wherein the first NPU is configured to operate based on a first phase of the first clock signal, and
the second NPU is configured to operate based on a second phase of the second clock signal so that two NPUs including the first NPU and the second NPU operate distributedly in different two phases including the first phase and second phase to reduce a peak power,
wherein a phase difference between the first and second clock signals is determined in consideration of a peak power of the SoC.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over Han (US Publication 20220004249 A1) and in view of Asano (US Publication US 20040041547 A1).
Regarding claim 1, Han discloses a system-on-chip (SoC) comprising:
a first circuitry [cluster 1220] provided for a first neural processing unit (NPU) configured to perform operations of a neural network (NN) model [0003, 0037, 0050: neural-network processing unit (NPU)];
a second circuitry [cluster 1230] provided for a second NPU configured to perform operations of a NN model [0003, 0037, 0050: neural-network processing unit (NPU)]; and
a clock signal supply circuit [DVFS 1210_1] configured to output one or more clock signals [0039] [0043] [0153],
wherein each of the first NPU and the second NPU includes a plurality of processing elements (PEs) [0003, 0037, 0050], wherein a first clock signal among the one or more clock signals, is supplied to the first NPU [0039] [0043] [0153], and a second clock signal among the one or more clock signals, is supplied to the second NPU [0039] [0043] [0153] [0045: Operations of the respective clusters 1230 and 1240 are similar to the operation of the cluster 1220 performed under control of the DVFS controller 1210_1, and thus, additional description will be omitted to avoid redundancy],
Han does not explicitly disclose (1) wherein at least one of the first and second clock signals has a preset phase (2) wherein the first NPU is configured to operate based on a first phase of the first clock signal, and the second NPU is configured to operate based on a second phase of the second clock signal, wherein a phase difference between the first and second clock signals is determined in consideration of a peak power of the SoC.
Asano discloses (1) wherein at least one of the first and second clock signals has a preset phase [0011: adjust phases of the clock signals provided to respective ones of the internal circuits] [0010-0013] [0050] [0060] [Figs.2, 8-10 and 12];
and (2) the first NPU is configured to operate based on a first phase of the first clock signal, and the second NPU is configured to operate based on a second phase of the second clock signal, wherein a phase difference between the first and second clock signals is determined in consideration of a peak power of the SoC [0011: A clock signal control circuit is connected to the power fluctuation measuring circuit to adjust phases of the clock signals provided to respective ones of the internal circuits so that the fluctuation peaks in the power supply voltage produced when the internal circuits are operated are substantially offset by one another] [0010-0013] [0050][0060] [Figs.2, 8-10 and 12].
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Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Han and Asano together because they both directed to adjust the clock signals to the processing circuits. Asano’s disclosing of adjusting phases of the clock signals provided to respective ones of the internal circuits so that the fluctuation peaks in the power supply voltage produced when the internal circuits are operated would allow Han to avoid voltage fluctuation or droop in the power supply when all or a lot of processing components operate at the same time.
Regarding claim 2, Asano discloses the SoC of claim 1, wherein the at least one of the first and second clock signals is generated by shifting, drifting, or delaying the phase of the original clock signal [0010-0013, Figs.8-10 and 12: delay circuits].
Regarding claim 3, Asano discloses the SoC of claim 1, wherein the second phase of the second clock signal is different from the first phase of the first clock signal [0010-0013, Figs.8-10 and 12: clocks with different phases, respectively].
Regarding claim 4, Asano discloses the SoC of claim 1, wherein the one or more clock signals include the first clock signal and the second clock signal, and wherein the first phase of the first clock signal is different from the second phase of the second clock signal, and the first phase of the first clock signal is same as a phase of the original clock signal [0010-0013][0034: The delay circuit 3 selects either the reference clock signal REFCLK or the output clock signal of one of the buffer circuits 4 and provides the selected clock signal Dout to the associated digital circuit] .
Regarding claim 5, Asano discloses the SoC of claim 1, wherein two NPUs including the first NPU and the second NPU operate distributedly in different two phases including the first phase and second phase to reduce a peak power [0010-0013] [0050] [0060] [Figs.8-10 and 12].
Regarding claim 6, Asano discloses the SoC of claim 1, wherein the at least one of the first and second clock signals has the preset phase based on a phase of an original clock signal [0010-0013] [0050] [0060] [Figs.8-10 and 12] [CLK1-CLKn are generated based on reference clock REFCLK].
Regarding claim 7, Asano discloses the SoC of claim 1, wherein the SoC further includes a third circuit for a third NPU, and a third clock signal among the one or more clock signals, is supplied to the third NPU [0010-0013] [0050] [0060] [Figs.2, 8-10 and 12][third clock signal is supplied to third digital circuit].
Regarding claim 8, Asano discloses the SoC of claim 1, wherein a number of the one or more clock signals is preset based on a number of NPUs [0010-0013] [0050] [0060] [Figs.2, 8-10 and 12] [CLK1-CLKn are generated based on number of digital circuits].
Regarding claim 10, Asano discloses the SoC of claim 1, further comprising: a semi-conductor substrate, wherein the first circuitry, the second circuitry and the clock signal supply circuit are disposed on the semi-conductor substrate [0030] [0061][semiconductor substrate].
Regarding claims 11-18, these claims are rejected for the same reasons as set forth in claims 1-8 above.
Regarding claim 19, Asano discloses the system of claim 11, further comprising a system bus, formed of an electrically conductive pattern, such that the first semi-conductor chip provided for the first NPU, the second semi-conductor chip provided for the second NPU, and the clock signal supply circuit communicate with each other [0030] [0061][semiconductor substrate].
Regarding claim 20, this claim is rejected for the same reasons as set forth in claim 1 above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Han (US Publication 20220004249 A1) and in view of Asano (US Publication US 20040041547 A1) and in further view of in view of Das Sarma et al (US Publication 2019/0235866 A1).
Regarding claim 9, Han and Asano do not disclose the SoC of claim 1, wherein the plurality of PEs include an adder, a multiplier, and an accumulator.
Das Sarma discloses the plurality of PEs include an adder, a multiplier, and an accumulator [0116: computation unit 1000 includes input values weight 1002, data 1004, and Resultln 1006; signals ClearAcc signal 1008, Clock signal 1010, ResultEnable signal 1012, ResultCapture signal 1014, and ShiftEn signal 1016; components accumulator 1024, multiplexer 1026, shadow register 1028, multiplier 1030, and adder 1032; logic 1034, 1036, and 1038; and output value ResultOut 1050].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Han, Asano and Das Sarma together because they directed to the plurality of processing units to execute instructions. Das Sarma’s disclosing of the plurality of PEs include an adder, a multiplier, and an accumulator would allow Han in view of Asano to increase the SoC’s integrity by enhancing the functions for the plurality of processing elements.
.
Allowable Subject Matter
In figure 10 and the corresponding texts of the specification contain the allowable subject matter. The application would be allowed if incorporating the feature below into the independent claims. The feature is disclosed in figure 10 and corresponding texts as follow: “a clock source provides an original clock signal to a phase shifter and wherein the phase shifter comprises a number of phase shifters or delay elements and multiplexer configured to output one or more clock signals based on signals from the number of phase shifters or delay elements”.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts do not disclose nor fairly suggest the proposed limitation above incorporated with other limitations as claimed in the independent claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m.
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/PHIL K NGUYEN/Primary Examiner, Art Unit 2176