DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This action is responsive to Applicant’s claims filed 08/29/2024.
Claims 1-20 are currently pending and have been examined here.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-8, 11-15, and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang et al. (U.S. PG Pub. No. 20250335741; hereinafter "Huang").
As per claim 1, Huang teaches:
A device, comprising:
Huang teaches a system and method for executing neural networks. (Huang: abstract)
a memory system, having: a host interface configured to pass control, address, and data signals between the memory system and a host system;
Huang teaches a memory system 502. (Huang: paragraph [0071], Fig. 5) Huang teaches a host interface in the form of processing engine array 510 connections to the other components of the system, wherein the host interface may pass control, address, and data signals between the processing engine and the memory system. (Huang: paragraph [0071], Fig. 5)
a volatile memory configured to have a plurality of regions accessible to the host system via the host interface;
Huang teaches a memory subsystem 504 with a plurality of memory regions 514. (Huang: paragraph [0071, 73-75], Fig. 5) Huang further teaches the use of volatile memory in order to perform the functions of the system. (Huang: paragraph [0183, 187-188])
and at least one processing device configured to perform computations of a neural network, wherein during a computation of the neural network, the memory system is operable to read first data from a first memory region of the plurality of regions in parallel with writing second data to a second memory region of the plurality of regions.
Huang teaches a processing device in the form of a processing engine 510 which may perform neural network computations of the system. (Huang: paragraph [0071-75], Fig. 5) Huang further teaches read and write commands into individual memory banks 514 of the system, wherein the read and write commands may be executed simultaneously (in parallel). (Huang: paragraphs [0071-76], Fig. 5)
As per claim 4, Huang teaches all of the limitations of claim 1, as outlined above, and further teaches:
wherein the plurality of regions correspond to a plurality of memory banks.
Huang further teaches read and write commands into individual memory banks 514 of the system, wherein the read and write commands may be executed simultaneously (in parallel). (Huang: paragraphs [0071-76], Fig. 5)
As per claim 5, Huang teaches all of the limitations of claim 1, as outlined above, and further teaches:
wherein the memory system further comprises: a plurality of controllers coupled to control the plurality of regions respectively.
Huang further teaches that the system may comprise a plurality of processing engines (controllers) connected to a plurality of regions respectively. (Huang: paragraph [0078-81], Fig. 5)
As per claim 6, Huang teaches all of the limitations of claim 5, as outlined above, and further teaches:
wherein the memory system further comprises: a plurality of parallel connections from the at least one processing device to the plurality of controllers respectively.
Huang further teaches that the system may comprise a plurality of processing engines (controllers) connected to a plurality of regions respectively, wherein each processing engine may be connected to another and may be executed in parallel. (Huang: paragraph [0078-81], Fig. 5)
As per claim 7, Huang teaches all of the limitations of claim 6, as outlined above, and further teaches:
wherein the memory system further comprises: a buffer configured to buffer data received via the host interface from the host system.
Huang further teaches a results buffer 512 which buffers data received over the host interface. (Huang: paragraph [0071], Fig. 5)
As per claim 8, Huang teaches the limitations of this claim which are substantially identical to those of claim 1, as outlined above, and further teaches:
A method, comprising:
Huang teaches a system and method for executing neural networks. (Huang: abstract)
As per claims 11-14, Huang teaches the limitations of these claims which are substantially identical to those of claims 4-7, and claims 11-14 are rejected for the same reasons as claims 4-7, as outlined above.
As per claim 15, Huang teaches the limitations of this claim which are substantially identical to those of claim 1, as outlined above, and further teaches:
A computing system, comprising:
Huang teaches a system and method for executing neural networks. (Huang: abstract) Huang further teaches the implementation of the system and method using one or more computing devices. (Huang: paragraph [0178-189], Fig. 15)
a host system;
Huang teaches a memory system 502. (Huang: paragraph [0071], Fig. 5) Huang teaches a host interface in the form of processing engine array 510 connections to the other components of the system, wherein the host interface may pass control, address, and data signals between the processing engine and the memory system. (Huang: paragraph [0071], Fig. 5)
and a memory system connected to the host system, having:
Huang teaches a memory system 502. (Huang: paragraph [0071], Fig. 5) Huang teaches a host interface in the form of processing engine array 510 connections to the other components of the system, wherein the host interface may pass control, address, and data signals between the processing engine and the memory system. (Huang: paragraph [0071], Fig. 5)
a volatile memory configured to have a plurality of regions accessible to the host system;
Huang teaches a memory subsystem 504 with a plurality of memory regions 514. (Huang: paragraph [0071, 73-75], Fig. 5) Huang further teaches the use of volatile memory in order to perform the functions of the system. (Huang: paragraph [0183, 187-188])
and at least one processing device configured to
Huang teaches a processing device in the form of a processing engine 510 which may perform neural network computations of the system. (Huang: paragraph [0071-75], Fig. 5)
As per claims 18-19, Huang teaches the limitations of these claims which are substantially identical to those of claims 4-5, and claims 18-19 are rejected for the same reasons as claims 4-5, as outlined above.
As per claim 20, Huang teaches all of the limitations of claim 19, as outlined above, and further teaches:
a plurality of parallel connections from the at least one processing device to the plurality of controllers respectively;
Huang further teaches that the system may comprise a plurality of processing engines (controllers) connected to a plurality of regions respectively, wherein each processing engine may be connected to another and may be executed in parallel. (Huang: paragraph [0078-81], Fig. 5)
a buffer configured to buffer data received from the host system.
Huang further teaches a results buffer 512 which buffers data received over the host interface. (Huang: paragraph [0071], Fig. 5)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-3, 9-10, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Merrill et al. (U.S. PG Pub. No. 20160335119; hereinafter "Merrill").
As per claim 2, Huang teaches all of the limitations of claim 1, as outlined above. With respect to the following limitation:
wherein the computation of the neural network is configured to train the neural network.
Huang teaches a processing device in the form of a processing engine 510 which may perform neural network computations of the system. (Huang: paragraph [0071-75], Fig. 5) Huang further teaches read and write commands into individual memory banks 514 of the system, wherein the read and write commands may be executed simultaneously (in parallel). (Huang: paragraphs [0071-76], Fig. 5) Huang, however, appears to teach that the read and write executions are performed in order to execute the neural network, rather than to train it.
Merrill, however, teaches simultaneous execution of read and write commands into different areas of memory in order to either execute or to train a neural network. (Merrill: paragraphs [0022-31]) It can be seen that each element is taught by either Huang or by Merrill. Performing the reading and writing into the memory banks of Huang during initial training of a neural network, as taught by Merrill does not affect the normal functioning of the elements of the claim which are taught by Huang. Because the elements do not affect the normal functioning of each other, the results of their combination would have been predictable. Therefore, before the effective filing date of the claimed invention, it would have been obvious to combine the teachings of Merrill with the teachings of Huang, since the result is merely a combination of old elements, and, since the elements do not affect the normal functioning of each other, the results of the combination would have been predictable.
As per claim 3, Haung in view of Merrill teaches all of the limitations of claim 2, as outlined above, and further teaches:
wherein the first data is representative of an input to the neural network;
Huang teaches that the read and write commands may be representative of input data 550 and output data in the form of results of calculations. (Huang: paragraph [0071-76, 86], Fig. 5)
and the second data is representative of an output from the neural network.
Huang teaches that the read and write commands may be representative of input data 550 and output data in the form of results of calculations. (Huang: paragraph [0071-76, 86], Fig. 5)
As per claims 9-10 and 16-17, Huang in view of Merrill teaches the limitations of these claims which are substantially identical to those of claims 2-3, and claims 9-10 and 16-17 are rejected for the same reasons as claims 2-3, as outlined above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMMETT K WALSH whose telephone number is (571)272-2624. The examiner can normally be reached Mon.-Fri. 6 a.m. - 4:45 p.m..
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/EMMETT K. WALSH/Primary Examiner, Art Unit 3626
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