DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Method of Manufacturing Semiconductor Device including Detecting Convex and Concave Defects in Surface Electrodes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Terasawa et al. JP/2011-108726, hereinafter “T1”, in view of Koga et al. US/2007-0076197 A1, hereinafter “K1”.
Regarding claim 1, T1 discloses, A method of manufacturing a semiconductor device, the method comprising:
as a first process, preparing a semiconductor wafer (T1 Fig 16E silicon substrate 101s) and forming a surface electrode ("as shown in FIG 16F, a metal film made of titanium (Ti), titanium nitride (TiN), tungsten (W), or the like on the silicon substrate 101s by using, for example, a sputtering method or a CVD method" [0103]) on a surface of the semiconductor wafer;
as a second process, forming a resist film (photoresist film (not shown) is deposited over the metal film layer [0103]) on the surface electrode;
as third process, exposing and developing the resist film ("a photoresist film patterned by EUV lithography (third lithography) is formed on the metal film (not shown), and the first wiring layer 116 is formed by an etching process" [0103]), thereby forming a resist pattern on the surface electrode;
and as a fourth process, detecting a surface defect, either:
using a difference of intensities of lights reflected from the resist pattern on the surface electrode between an area thereof where the surface defect occurs and an area thereof where no surface defect occurs by irradiating light on the resist pattern on the surface electrode (light scattered at the edge of the absorber pattern is also captured, and only a small signal can be obtained as compared with the bright spot of the phase defect. However, when a defect exists in the absorber pattern, the intensity of the detection signal changes" [0037]),
or using a comparison between a surface image of the area where the surface defect occurs and a surface image of the surface where no surface defect occurs by photographing the surface of the semiconductor wafer using a photographing mechanism (T1 Fig 9 is a time chart that discloses the process of inspecting and comparing images taken in a die-to-die comparison of the EUV mask M; "The comparison circuit 9 compares the two inspection image data (pixel signal data) according to an appropriate algorithm, and if the difference is larger than a predetermined threshold value (predetermined threshold value), the two are not matched, so that it is determined that there is a defect"[0061]),
wherein the third process includes causing a deficient pattern portion to occur in a portion of the resist pattern at the surface defect (Fig 5 displays five types of defects present in the resist pattern at the location of surface defects; these defects create the deficient pattern portions shown),
and the fourth process includes detecting a position (step S107 [Abstract]) of the deficient pattern portion at the resist pattern as a focal point of the lights irradiated (Fig 24, light source 80 emits light that is then focused on the wafer 83) or a focal point of the photographing mechanism (T1 discloses the comparison of pixel images of the inspection regions, obtained by an image detector, inherently using a means of photography [Abstract]) and determining a detected position of the deficient pattern portion as a detection position of the surface defect ("when the defect is detected in the inspection area on the EUV mask, the position of the inspection area is recorded as a relative position from the reference mark [Claims step G]).
T1 fails to explicitly disclose detecting a surface defect occurring in the surface electrode during the first process, T1 detects surface defects on the surface of a multilayer film mask, but fails to disclose using their inspection methods on a surface electrode during its formation.
However, in the same field of endeavor, K1 discloses a device manufacturing method that includes detecting a surface defect occurring in the surface electrode during the first process (K1 Fig 22 the wafer process step S4 includes the forming of an electrode on the wafer [0168] then inspecting the wafer for foreign particles.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the wafer inspected in T1 with the wafer containing the surface electrode as disclosed in K1 to manufacturing semiconductor devices with inspection systems for multiple wafer structures that can all achieve high throughput and accuracy [K1 0011].
Regarding claim 5, T1 in view of K1 discloses The method of manufacturing according to claim 1, wherein the third process includes forming on the surface electrode (electrode of K1 [0168]) without the defect, the resist pattern to have regularity or forming repeating patterns (T1 Fig 3b, absorption patterns ABS repeat at regular repeating intervals of 140 nm [0044]).
Regarding claim 6, T1 in view of K1 discloses The method of manufacturing according to claim 1, wherein the third process includes forming the resist pattern in which a total area of the resist left portions is equal to a total area of the resist removed portions on the surface electrode without the defect (T1 Fig 3b and 25b, the resist patterns (absorption patterns ABS) where the "width and interval" are both 140 nm; therefore, disposed at regular intervals with total equal areas of left and removed portions [0044]).
Regarding claim 7, T1 in view of K1 discloses The method of manufacturing according to claim 1, wherein the surface defect includes a convex defect in which a portion of a surface of the surface electrode is raised, or a concave defect in which a portion of the surface of the surface electrode is recessed, or both the convex defect and the concave defect (Fig 25a-25b give examples of convex and concave defects, respectively), and the third process includes, setting, as a focal point of the exposing, a surface of a first portion of the resist film on the surface without the surface defect, and performing the exposing the resist film using light having a short wavelength (film is exposed to extreme ultraviolet light (EUV) "LL having a central wavelength of 13.5 nm emitted from the light source 80" [0031]) so that the focal point of the exposing is not aligned with a surface of a second portion of the resist film on the surface defect (T1 Fig 24 shows light from light source 80 focusing on the top surface of the wafer 83) to thereby form the resist pattern that has different patterns between the surface without the surface defect and the surface with the surface defect (defects’ effect on the patterns ABS shown in T1 Fig 5 and Fig 12).
Regarding claim 8, T1 in view of K1 discloses The method of manufacturing according to claim 7, wherein the first process includes: depositing the surface electrode by sputtering (T1 metal film sputtered [0103]), and patterning the surface electrode by photolithography and etching (T1 [0103], first wiring layer 116 is formed by an etching process), the convex defect occurs due to foreign matter being incorporated in the surface electrode during the depositing (T1 [0031] Fig 25A "a convex phase defect 91 is generated because fine particles P01 are sandwiched when the multilayer film ML is deposited on the substrate MS"), the concave defect occurs due to the surface electrode being selectively removed at a deficient resist portion of a resist mask used during the etching (T1 [0031] Fig 25B "concave phase defect 92 is generated as a result of depositing the multilayer film ML with the minute depression P02 existing on the substrate MS").
Regarding claim 9, T1 in view of K1 discloses The method of manufacturing according to claim 1, wherein the third process includes forming the resist pattern for each of a plurality of chip regions provided with regularity on the semiconductor wafer (T1 discloses "the comparison circuit 6 compares the images of the two dies 51 and 52 (two chips A1 and A2) to determine whether there is a defect" [0066]), and the fourth process includes photographing the surface of the semiconductor wafer using the photographing mechanism and comparing images of two adjacent ones of the plurality of chip regions of the semiconductor wafer ([0066] describes taking an inspection image of the second chip and comparing that data to the inspection image stored in the pattern memory for the first chip).
Claim(s) 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over T1 in view of K1, further in view of Himoto et al. CN/112189379 A, hereinafter “H1”.
Regarding claim 2, T1 in view of K1 discloses The method of manufacturing according to claim 1, wherein forming the resist pattern (T1 absorber pattern ABS Fig 12) includes forming a plurality of resist left portions (ABS columns colored in grey Fig 12) and a plurality of resist removed portions (reflection regions REF Fig 12) on the surface electrode without the defect, but T1 in view of K1 fails to explicitly disclose the width of the deficient pattern portion.
T1 in view of K1 do not explicitly disclose, setting each of the plurality of resist left portions to have smaller in size in a predetermined direction parallel to the surface of the semiconductor wafer than a width of the deficient pattern, or setting each of the plurality of resist removed portions to have smaller in size in the predetermined direction than a width of the deficient pattern portion.
However, in the same field of endeavor, H1 discloses a manufacturing method including the removal of foreign particles ranging in diameter or height from 1 to 5 microns [H1 Fig 1 element 30 [0004]]. H1 discloses the width of the deficient pattern portion corresponds to the width of the foreign particle present on the device surface (H1 Fig 1 and Fig 6), and that the typical diameter or height of such foreign particles is around 1 to 5 microns.
Therefore, T1 in view of K1 with support from the disclosure of H1 discloses setting each of the plurality of resist left portions to have smaller in size in a predetermined direction parallel to the surface of the semiconductor wafer than a width of the deficient pattern (T1 [0044] discloses "the width and interval of the absorber pattern ABS are both 140 nm." ; while, H1 discloses that the particle size of foreign particles being between 1 – 5 microns; therefore, the width of T1’s ABS pattern is smaller than the diameter and height of common foreign particles), or setting each of the plurality of resist removed portions to have smaller in size in the predetermined direction than a width of the deficient pattern portion (the width of the resist left and resist removed portion of the ABS pattern in T1 are equal).
Regarding claim 3, T1 in view of K1 with support from the disclosure of H1 disclose The method of manufacturing according to claim 2, wherein a width of the resist left portion (T1 140 nm) of the resist pattern on the surface electrode without the defect in the predetermined direction is narrower than a width of the surface defect (width of surface defect, given by H1: 1 – 5 microns; the width of the resist left portion ABS in T1 at 140 nm is narrower than the disclosed foreign particle diameter or height in H1), and the width of the resist removed portion of the resist pattern on the surface electrode without the defect is narrower than the width of the surface defect (the width of the resist left and resist removed portion of the ABS pattern in T1 are equal; both are narrower than 1 – 5 microns).
Regarding claim 4, T1 in view of K1 with support from the disclosure of H1 disclose The method of manufacturing according to claim 2, wherein a width of the resist left portion of the resist pattern on the surface electrode without the defect is not more than ¼ of the width of the surface defect (see examiner note below), and the width of the resist removed portion of the resist pattern on the surface electrode without the defect is not more than ¼ of the width of the surface defect (the 140 nm width of the resist left and resist removed ABS pattern regions in T1 are both less than a quarter of the width of the range of widths of foreign particles as disclosed in H1, 1 - 5 microns).
Furthermore, pertaining to the claimed limitation of a width of the resist left portion of the resist pattern on the surface electrode without the defect is not more than ¼ of the width of the surface defect: the instant application [instant 0068] discloses the width of foreign matter particles to be about 7 microns or more. The instant application [instant 0071] also discloses the overall deficient pattern portion has a size of about 11 microns for a convex defect and about 21 microns or more for a concave defect. Therefore, in light of the specification, T1 in view of K1, meets the limitation of claim 4 because T1’s resist left and resist removed portion having a width of 140 nm is far less than a quarter of 7 microns, or 7000 nm, for the width of a “foreign matter” as disclosed by the instant application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fujimori et al. WO/2012-063859 A1 which discloses a substrate inspection method using image comparison and illumination intensity data
Yu et al. US/2019-0064675 A1 which discloses methods of defect inspection and the effects of such defects in Figs 2E – 2H
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA MICKEY whose telephone number is (571)270-3109. The examiner can normally be reached M-F, 8am to 5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at 571 270 7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TERESA N MICKEY/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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