Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Specification
The disclosure is objected to because of the following informalities: Paragraph [00235], in line 2, comprises a duplicate recitation, “run at a at a highest privilege level”. Appropriate correction is required.
Claim Interpretation
Claims 1, 12, and 19 comprise the limitation, “wherein interrupt service routines (ISRs) are not employed to handle the respective interrupts”. Paragraph [00238] of the instant Specification defines “handling” as: “Handling an interrupt by an IST 1010 refers to the IST 1010 performing designated actions in response to the interrupt, where the designated actions can differ depending upon the type of interrupt (e.g., the interrupt source 1012)” (emphasis added).
The performance of designation actions being based upon the type of interrupt represents that the “handling” of the interrupt is directed to the processing of the interrupt. Therefore, while Comeau (Paragraph 48) discusses ISR 80 activating interrupt service threads 84-88 upon receiving an interrupt, this is not considered “handling” the interrupt as the IST’s are performing the handling/processing of the interrupt (See Paragraph 50; “Processing of the interrupt is deferred to the interrupt service thread.”).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed, approved immediately upon submission, and reduces waiting time for Terminal Disclaimer to be manually approved. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over Claims 1-9 and 11-20 of U.S. Patent No. 12,106,141, since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent. Although the conflicting claims are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is at least fully disclosed in the reference patent, as follows:
U.S. Application No. 18/819,753 Claims
U.S. Patent No. 12,106,141 Claims
1. A system comprising: one or more hardware processors; a plurality of threads executable on the one or more hardware processors and comprising interrupt service threads to handle respective interrupts, wherein the plurality of threads are assigned respective priorities, and wherein a first thread associated with an application program has a first priority that is higher than a second priority of a first interrupt service thread of the interrupt service threads; and a kernel scheduler executable on the one or more hardware processors to: schedule execution of the plurality of threads based on the respective priorities assigned the plurality of threads, wherein interrupt service routines (ISRs) are not employed to handle the respective interrupts.
1. A system comprising: one or more hardware processors; a plurality of threads executable on the one or more hardware processors and comprising a first thread associated with an application program, and interrupt service threads to handle respective interrupts, wherein the plurality of threads are assigned respective priorities such that the first thread associated with the application program has a first priority that is higher than a second priority of a first interrupt service thread of the interrupt service threads, and the first priority of the first thread associated with the application program is lower than a third priority of a second interrupt service thread of the interrupt service threads; and a kernel scheduler executable on the one or more hardware processors to: determine the first priority of the first thread associated with the application program, and the second priority of the first interrupt service thread executed on a first hardware processor, and schedule the first thread and the first interrupt service thread based on the first priority and the second priority by preempting the first interrupt service thread to schedule the first thread for execution on the first hardware processor based on the first thread having the first priority that is higher than the second priority, wherein the preempting of the first interrupt service thread switches the first interrupt service thread from an active state to a ready state in which the first interrupt service thread is placed in a queue.
3. The system of claim 1, wherein interrupt service routines (ISRs) are not employed to handle the respective interrupts.
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12. A method of a system comprising one or more hardware processors, comprising: receiving, by a scheduling executive of an operating system (OS) kernel executing on the one or more hardware processors, a call from a first thread of an application program, wherein the first thread has a first priority, and wherein the system comprises a plurality of threads comprising the first thread of the application program and interrupt service threads to handle respective interrupts, and wherein the plurality of threads are assigned respective priorities such that the first priority of the first thread of the application program is higher than a second priority of a first interrupt service thread of the interrupt service threads; associating the interrupt service threads with respective interrupt sources; receiving, by the scheduling executive executing on the one or more hardware processors, an indication of an interrupt from an interrupt source of the interrupt sources, wherein the first interrupt service thread is executable on a first hardware processor to handle the interrupt from the interrupt source; and scheduling, by the scheduling executive executing on the one or more hardware processors, execution of the plurality of threads based on the respective priorities assigned the plurality of threads, wherein interrupt service routines (ISRs) are not employed to handle the respective interrupts.
12. A method of a system comprising one or more hardware processors, comprising: receiving, by a scheduling executive of an operating system (OS) kernel executing on the one or more hardware processors, a call from a first thread of an application program, wherein the first thread has a first priority, and wherein the system comprises a plurality of threads comprising the first thread of the application program and interrupt service threads to handle respective interrupts, and wherein the plurality of threads are assigned respective priorities such that the first priority of the first thread of the application program is higher than a second priority of a first interrupt service thread of the interrupt service threads, and the first priority of the first thread of the application program is lower than a third priority of a second interrupt service thread of the interrupt service threads; associating the interrupt service threads with respective interrupt sources; receiving, by the scheduling executive executing on the one or more hardware processors, an indication of an interrupt from an interrupt source of the interrupt sources, wherein the first interrupt service thread is executable on a first hardware processor to handle the interrupt from the interrupt source; and scheduling, by the scheduling executive executing on the one or more hardware processors, the first thread having the first priority and the first interrupt service thread having the second priority, wherein the scheduling comprises preempting the first interrupt service thread with the first thread based on the first thread having the first priority that is higher than the second priority, and wherein the preempting of the first interrupt service thread switches the first interrupt service thread from an active state to a ready state in which the first interrupt service thread is placed in a queue containing threads to be scheduled by the scheduling executive for execution on the first hardware processor.
18. The method of claim 12, wherein interrupt service routines (ISRs) are not employed to handle the respective interrupts.
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19. A non-transitory machine-readable storage medium comprising instructions that upon execution cause a system to: receive, at a scheduling executive of an operating system (OS) kernel, a call from a non-interrupt service thread, wherein the non-interrupt service thread has a first priority, and wherein the system comprises a plurality of threads comprising the non-interrupt service thread and interrupt service threads, the interrupt service threads to handle respective interrupts, and wherein the plurality of threads are assigned respective priorities such that the first priority of the non-interrupt service thread is higher than a second priority of a first interrupt service thread of the interrupt service threads; receive, at the scheduling executive, a notification of an interrupt from an interrupt source, wherein the interrupt is associated with the first interrupt service thread executable on a first hardware processor to handle the interrupt; and schedule, by the scheduling executive, the non-interrupt service thread and the first interrupt service thread based on the first priority and the second priority, wherein the scheduling comprises preempting the first interrupt service thread with the non-interrupt service thread based on the non-interrupt service thread having the first priority that is higher than the second priority, wherein interrupt service routines (ISRs) are not employed to handle the respective interrupts.
19. A non-transitory machine-readable storage medium comprising instructions that upon execution cause a system to: receive, at a scheduling executive of an operating system (OS) kernel, a call from a non-interrupt service thread, wherein the non-interrupt service thread has a first priority, and wherein the system comprises a plurality of threads comprising the non-interrupt service thread and interrupt service threads, the interrupt service threads to handle respective interrupts, and wherein the plurality of threads are assigned respective priorities such that the first priority of the non-interrupt service thread is higher than a second priority of a first interrupt service thread of the interrupt service threads, and the first priority of the non-interrupt service thread is lower than a third priority of a second interrupt service thread of the interrupt service threads; receive, at the scheduling executive, a notification of an interrupt from an interrupt source, wherein the interrupt is associated with the first interrupt service thread executable on a first hardware processor to handle the interrupt; and schedule, at the scheduling executive, the non-interrupt service thread and the first interrupt service thread based on the first priority and the second priority, wherein the scheduling comprises preempting the first interrupt service thread with the non-interrupt service thread based on the non-interrupt service thread having the first priority that is higher than the second priority, and wherein the preempting of the first interrupt service thread switches the first interrupt service thread from an active state to a ready state in which the first interrupt service thread is placed in a queue containing threads to be scheduled by the scheduling executive for execution on the first hardware processor.
3. The system of claim 1, wherein interrupt service routines (ISRs) are not employed to handle the respective interrupts.
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 4-7, 10, 12, 13, 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Comeau et al. U.S. PGPUB No. 2002/0161957 in view of Jin et al. U.S. PGPUB No. 2018/0275891. (all cited in the IDS dated 8/29/2024)
Per Claim 1, Comeau discloses a system comprising:
one or more hardware processors (Fig. 2A, processor core 10);
a plurality of threads executable on the one or more hardware processors and comprising interrupt service threads to handle respective interrupts (Paragraph 36; IST’s 84-88),
wherein the plurality of threads are assigned respective priorities (Paragraph 38, Figure 3; Thread status table 110 indicates a priority for each thread.),
and a kernel scheduler executable on the one or more hardware processors (scheduler 90) to:
schedule execution of the plurality of threads based on the respective priorities assigned the plurality of threads (Paragraphs 35-46),
wherein interrupt service routines (ISRs) are not employed to handle the respective interrupts (Paragraph 14; “In order to simplify the processing of interrupts received in a processing environment such as a Java or Java like processing environment, rather than having interrupt service routines run by an operating system, a scheduler is provided for performing thread switching between various application layer threads, the application layer threads including application layer threads designated to handle interrupts”. Paragraph 50; “Processing of the interrupt is deferred to the interrupt service thread.”).
Comeau teaches (Paragraph 38 and Figure 3) that the interrupt service threads are given a higher priority than the java application threads, as opposed to the claimed application threads having priority over interrupt service threads. However, Comeau also states (Paragraph 38) that “Many prioritization schemes may of course be employed”, which implies that various embodiments utilizing different prioritization schemes with respect to the threads may be implemented.
Jin teaches optimizing workload/application process priority such that the highest priority is assigned to the workload/application threads (Paragraphs 29, 44, and 52).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the application thread prioritization scheme of Jin as one of the “many prioritization schemes” of Comeau because a system design may wish to optimize different system aspects, such as latency and performance (Jin, Paragraphs 44 and 52).
Per Claim 2, Comeau discloses the system of claim 1, wherein the scheduling of the execution of the plurality of threads based on the respective priorities comprises: preempting the first interrupt service thread executed on a first hardware processor to schedule the first thread associated with the application program for execution on the first hardware processor based on the first thread having the first priority that is higher than the second priority (Paragraphs 18-21, 38, 45, 46, 50, 51, Figure 3; thread status table 110). Please refer to the above rejection of claim 1 which discusses Jin teaching assigning a highest priority to an application thread among other threads.
Per Claim 4, Comeau discloses the system of claim 2, wherein the preempting of the first interrupt service thread switches the first interrupt service thread from an active state to a ready state in which the first interrupt service thread is placed in a queue (Paragraph 45; If the thread schedule 90 determines from the thread status table 110 that there is a thread with QUEUED status which has a higher priority than the thread which is current RUNNING, then scheduler 90 will trigger a preemption and perform a thread switch. The scheduler 90 changes the status of the previously RUNNING thread to QUEUED.).
Per Claim 5, Comeau discloses the system of claim 1, wherein the kernel scheduler is executable on the one or more hardware processors to: based on a notification of an interrupt, identify an interrupt source of the interrupt (Paragraphs 35, 48, 49, and 56-58).
Per Claim 6, Comeau discloses the system of claim 5, wherein the kernel scheduler is executable on the one or more hardware processors to identify the interrupt source of the interrupt by issuing a function executed by a processing device of the system (Paragraphs 48, 49, 56; interrupt service table 100 and interrupt source descriptor table 214).
Per Claim 7, Comeau discloses the system of claim 5, wherein the kernel scheduler is to: based on identifying the interrupt source, identify a plurality of interrupt service threads associated with the interrupt source (Paragraphs 48 and 49).
Per Claim 10, Comeau discloses the system of claim 1, wherein the kernel scheduler is executable on the one or more hardware processors to: preempt a second thread having a third priority lower than the second priority, and responsive to the preemption of the second thread, schedule the interrupt service thread for execution (Paragraphs 45, 46, 50, and 51; An interrupt service thread is shown to have a higher priority than an application thread and allow preemption of it. Similar to the rejection of claim 1, it would have been obvious to have different priorities assigned to a plurality of different types of threads.).
Per Claim 12, Comeau discloses:
a method of a system comprising one or more hardware processors (Fig. 2A, processor core), comprising:
receiving by a scheduling executive of an operating system (OS) kernel executing on the one or more hardware processors (scheduler 90), a call from a first thread of an application program, wherein the first thread as a first priority (Paragraphs 9 and 36-38; java application threads 82/83);
and wherein the system comprises a plurality of threads comprising the first thread of the application program and interrupt service threads to handle respective interrupts, and wherein the plurality of threads are assigned respective priorities (Paragraph 36; IST’s 84-88; Paragraph 38, Figure 3; Thread status table 110 indicates a priority for each thread.),
associating the interrupt service threads with respective interrupt sources (Paragraphs 36, 38, and 48; Interrupt service table 100);
receiving, by the scheduling executive executing on the one or more hardware processors, an indication of an interrupt from an interrupt source of the interrupt sources, wherein the first interrupt service thread is executable on a first hardware processor to handle the interrupt from the interrupt source (Paragraphs 48, 49, 56; interrupt service table 100 and interrupt source descriptor table 214);
and scheduling, by the scheduling executive executing on the one or more hardware processors, execution of the plurality of threads based on the respective priorities assigned the plurality of threads (Paragraphs 36-45),
wherein interrupt service routines (ISRs) are not employed to handle the respective interrupts (Paragraph 14; “In order to simplify the processing of interrupts received in a processing environment such as a Java or Java like processing environment, rather than having interrupt service routines run by an operating system, a scheduler is provided for performing thread switching between various application layer threads, the application layer threads including application layer threads designated to handle interrupts”. Paragraph 50; “Processing of the interrupt is deferred to the interrupt service thread.”).
Comeau teaches (Paragraph 38 and Figure 3) that the interrupt service threads are given a higher priority than the java application threads, as opposed to the claimed application threads having priority over interrupt service threads. However, Comeau also states (Paragraph 38) that “Many prioritization schemes may of course be employed”, which implies that various embodiments utilizing different prioritization schemes with respect to the threads may be implemented.
Jin teaches optimizing workload/application process priority such that the highest priority is assigned to the workload/application threads (Paragraphs 29, 44, and 52).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the application thread prioritization scheme of Jin as one of the “many prioritization schemes” of Comeau because a system design may wish to optimize different system aspects, such as latency and performance (Jin, Paragraphs 44 and 52).
Per Claims 13, please refer to the above rejection of claims 2, as the limitations are substantially similar and the mapping of the limitations to the reference is equally applicable.
Per Claim 15, Comeau discloses the method of claim 12, wherein the first thread is a non-interrupt service thread (Paragraph 36; Java applications A/B 82/83).
Per Claim 19, Comeau discloses:
a non-transitory machine-readable storage medium comprising instructions that upon execution cause a system (Paragraph 22; “hardware in combination with suitable internally or externally store software, etc.” represents a computer readable storage medium embodiment) to:
receive, at a scheduling executive of an operating system (OS) kernel (scheduler 90),
a call from a non-interrupt service thread, wherein the non-interrupt service thread has a first priority (Paragraphs 9 and 36-38; java application threads 82/83),
and wherein the system comprises a plurality of threads comprising the non-interrupt service thread and interrupt service threads, the interrupt service threads to handle respective interrupts, and wherein the plurality of threads are assigned respective priorities (Paragraph 36; IST’s 84-88; Paragraph 38, Figure 3; Thread status table 110 indicates both non-interrupt service threads (Java Application) and IST’s, and a priority for each thread.);
receive, at the scheduling executive, a notification of an interrupt from an interrupt source, wherein the interrupt is associated with the first interrupt service thread executable on a first hardware processor (Fig. 2A, processor core) to handle the interrupt (Paragraphs 48, 49, 56; interrupt service table 100 and interrupt source descriptor table 214);
and schedule, by the scheduling executive, the non-interrupt service thread and the first interrupt service thread based on the first priority and the second priority (Paragraphs 36-45),
wherein the scheduling comprises preempting the first interrupt service thread with the non-interrupt service thread based on the priorities assigned to each thread (Paragraphs 18-21, 38, 45, 46, 50, 51, Figure 3; thread status table 110),
wherein interrupt service routines (ISRs) are not employed to handle the respective interrupts (Paragraph 14; “In order to simplify the processing of interrupts received in a processing environment such as a Java or Java like processing environment, rather than having interrupt service routines run by an operating system, a scheduler is provided for performing thread switching between various application layer threads, the application layer threads including application layer threads designated to handle interrupts”. Paragraph 50; “Processing of the interrupt is deferred to the interrupt service thread.”).
Comeau teaches (Paragraph 38 and Figure 3) that the interrupt service threads are given a higher priority than the java application threads, as opposed to the claimed application threads having priority over interrupt service threads. However, Comeau also states (Paragraph 38) that “Many prioritization schemes may of course be employed”, which implies that various embodiments utilizing different prioritization schemes with respect to the threads may be implemented.
Jin teaches optimizing workload/application process priority such that the highest priority is assigned to the workload/application threads (Paragraphs 29, 44, and 52).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the application thread prioritization scheme of Jin as one of the “many prioritization schemes” of Comeau because a system design may wish to optimize different system aspects, such as latency and performance (Jin, Paragraphs 44 and 52).
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Claims 3, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Comeau et al. U.S. PGPUB No. 2002/0161957 in view of Jin et al. U.S. PGPUB No. 2018/0275891 in further view of Shaylor, U.S. PGPUB No. 2004/0117793. (all cited in the IDS dated 8/29/2024)
Per Claims 3 and 14, Comeau does not expressly teach migrating a preempted thread to a second processor upon it becoming available.
However, Shaylor teaches thread preemption (Paragraphs 54 and 55) and migrating threads to an available processor in concert with preemption (Paragraphs 10, 80, and 84).
Additionally, Jin teaches at least two CPU’s included within the server 102 (Paragraphs 34-36).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include Shaylor’s multiple processors and thread migration within the system of Comeau/Jin because it would lead to increased productivity due to multiple processors executing multiple threads at a time.
Per Claim 20, Comeau does not expressly teach migrating a preempted thread to a second processor upon it becoming available, and migrating a preempted thread to a second processor upon it becoming available, or wherein the preempted first interrupt service thread is associated with a context comprising a register set and a stack area, and wherein the migrating of the first interrupt service thread comprises migrating the context from the first hardware processor to the second hardware processor.
However, Shaylor teaches thread preemption (Paragraphs 54 and 55), migrating threads to an available processor in concert with preemption (Paragraphs 10, 80, and 84), and wherein the preempted first interrupt service thread is associated with a context comprising a register set and a stack area, and wherein the migrating of the first interrupt service thread comprises migrating the context from the first hardware processor to the second hardware processor (Paragraphs 31 and 33).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include Shaylor’s multiple processors and thread migration within the system of Comeau/Jin because it would lead to increased productivity due to multiple processors executing multiple threads at a time.
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Claims 8, 9, 11, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Comeau et al. U.S. PGPUB No. 2002/0161957 in view of Jin et al. U.S. PGPUB No. 2018/0275891 in further view of Ishida et al. U.S. PGPUB No. 2018/0293095. (all cited in the IDS dated 8/29/2024)
Per Claims 8 and 9, Comeau does not specifically disclose the use of semaphores.
However, Ishida discloses assigning a semaphore with an interrupt (Paragraph 162) and transitioning a task/thread from a blocked state to a ready state (Paragraphs 251-255).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement Ishida’s semaphore teachings within the invention of Comeau/Jin because semaphores are effective in multi-threaded systems to ensure that shared resources are not “double-booked” which can create a coherency problem.
Per Claims 11 and 16, Comeau does not specifically disclose the use of semaphores.
However, Ishida discloses assigning a semaphore with an interrupt (Paragraph 162) and transitioning a task/thread from a blocked state to a ready state through the use of incrementing/decrementing semaphore counters (Paragraphs 251-255).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement Ishida’s semaphore teachings within the invention of Comeau/Jin because semaphores are effective in multi-threaded systems to ensure that shared resources are not “double-booked” which can create a coherency problem.
Per Claim 17, Comeau discloses identifying, by the scheduling executive executing on the one or more hardware processors, a plurality of interrupt service threads associated with the interrupt source (Paragraphs 48, 49, 56; interrupt service table 100 and interrupt source descriptor table 214).
Comeau does not specifically teach signaling, by the scheduling executive executing on the one or more hardware processors, semaphores associated with the identified plurality of interrupt service threads.
However, Ishida discloses assigning a semaphore with an interrupt (Paragraph 162).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement Ishida’s semaphore teachings within the invention of Comeau/Jin because semaphores are effective in multi-threaded systems to ensure that shared resources are not “double-booked” which can create a coherency problem.
Per Claim 18, Comeau does not specifically teach transitioning, by the scheduling executive executing on the one or more hardware processors, each interrupt service thread of the identified plurality of interrupt service threads blocked on an associated semaphore to a ready state for scheduling.
However, However, Ishida discloses assigning a semaphore with an interrupt (Paragraph 162) and transitioning a task/thread from a blocked state to a ready state through the use of incrementing/decrementing semaphore counters (Paragraphs 251-255).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement Ishida’s semaphore teachings within the invention of Comeau/Jin because semaphores are effective in multi-threaded systems to ensure that shared resources are not “double-booked” which can create a coherency problem.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889 - (Direct Fax: 571-273-0889). The examiner can normally be reached on M-F: 8-4:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Brian T Misiura/
Primary Examiner, Art Unit 2175