DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
PNG
media_image1.png
659
829
media_image1.png
Greyscale
Claims 1-6, 8-14, and 17-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (KR 20230103590 A), hereinafter referred to as "Lee".
Regarding claim 1, Lee discloses a display apparatus, comprising: a substrate that includes a pixel (211 in Lee figure 2); a light-emitting diode in the pixel (230 in figure 2); a first insulating layer around the light-emitting diode (213 in figure 2; it is on both sides and of the diode, and thus is around it; it is also in close proximity to the diode, and thus is around the diode); a second insulating layer on the first insulating layer (215 in figure 2); and a first bank around the second insulating layer (219 in figure 2; it is in close proximity to and thus is around the second insulating layer).
Regarding claim 2, Lee discloses all of the limitations of claim 1, and further discloses a thin-film transistor on the substrate (220 in figure 2), wherein the first bank covers at least a portion of the thin-film transistor (219 covers all of the transistor 220 in figure 2).
Regarding claim 3, Lee discloses all of the limitations of claim 1, and further discloses a connection electrode on the first insulating layer (242 in figure 2); and a second bank on the connection electrode (216 in figure 2).
Regarding claim 4, Lee discloses all of the limitations of claim 1, and further discloses a reflective layer under the light-emitting diode (243 in figure 2).
Regarding claim 5, Lee discloses all of the limitations of claim 3, and further discloses a hole in the second insulating layer (contact holes formed in 215 on left and right of the LED see Lee translation page 7 first paragraph), wherein the second bank is in the hole (216 is in the contact hole in figure 2).
Regarding claim 6, Lee discloses all of the limitations of claim 3, and further discloses a hole extending through the second insulating layer and a part of the first insulating layer (contact holes formed in 215 on left and right of the LED, see Lee translation page 7 first paragraph. It also goes through 213), wherein the second bank is in the hole (216 is in the contact hole in figure 2).
Regarding claim 8, Lee discloses all of the limitations of claim 3, and further discloses that the second bank is on a plurality of sides of the light-emitting diode (second bank 216 is on at least the left and right sides of the light-emitting diode 230 in figure 2, and thus a plurality of sides).
Regarding claim 9, Lee discloses all of the limitations of claim 1, and further discloses a connection electrode on the first insulating layer (241 in figure 2), wherein the first bank is on the connection electrode (219 is on top of 241 in figure 2).
Regarding claim 10, Lee discloses all of the limitations of claim 9, and further discloses a thin-film transistor on the substrate (220 in figure 2), wherein the first bank covers the thin-film transistor (219 covers all of 220 in figure 2).
Regarding claim 11, Lee discloses all of the limitations of claim 9, and further discloses a second bank under the light-emitting diode (216, which is a least partially under the light-emitting diode 230 in figure 2), wherein the first bank overlaps with opposing ends of the second bank in an upper direction and a lower direction that is opposite to the upper direction (219 overlaps both left and right ends of 216 in the up and down directions in figure 2).
Regarding claim 12, Lee discloses all of the limitations of claim 11, and further discloses that the second bank extends outside of the light-emitting diode (the second bank is not inside the diode at all and thus extends entirely outside of the light-emitting diode).
Regarding claim 13, Lee discloses all of the limitations of claim 1, and further discloses a second bank on the first insulating layer (216 in figure 2), and the second bank is on a portion of a side surface of the light-emitting diode (it is on portions of the left side and the right sides in figure 2).
Regarding claim 14, Lee discloses all of the limitations of claim 13, and further discloses that the first bank overlaps with a side end of the second bank in an upper direction and a lower direction that is opposite to the upper direction (216 and 219 overlap with their side ends in figure 2).
Regarding claim 17, Lee discloses all of the limitations of claim 13, and further discloses that a first vertical level of an upper end of a portion of the second bank that is adjacent to a first side of the light-emitting diode is higher than a second vertical level of an upper end of a portion of the second bank that is adjacent to a second side of the light-emitting diode (vertical level of the flat horizontal upper end of the second bank 216 is higher than the vertical level of the angled upper end of the second bank. Since both are adjacent and on both sides of the light-emitting device, one will be on one side, and the other will be on a second side).
Regarding claim 18, Lee discloses all of the limitations of claim 13, and further discloses a connection electrode on the first insulating layer (242 in figure 2), wherein a side surface of the light-emitting diode is in contact with the first insulating layer, the second bank, and the connection electrode (the side surface of the diode is in electrical contact with the connection electrode, and in thermal contact with the insulating layer, second bank, and connection electrode, via the connection electrode).
Regarding claim 19, Lee discloses all of the limitations of claim 13, and further discloses that the second bank includes an inclined surface and a flat surface that are connected to each other (inclined surfaces and horizontal flat surfaces of bank 216 in the contact hole which are connected to each other), and wherein a horizontal spacing between the inclined surface and a side surface of the light-emitting diode varies as the inclined surface extends from an upper end of the inclined surface to a lower end of the inclined surface (distance to the diode increases going down the inclined surface, and thus varies).
Regarding claim 20, Lee discloses all of the limitations of claim 13, and further discloses that the first bank is on the second insulating layer (219 is on top of 215), and wherein the second bank is on the first insulating layer (216 is on top of 213).
Regarding claim 21, Lee discloses all of the limitations of claim 13, and further discloses a reflective layer under the light-emitting diode (243 in figure 2).
PNG
media_image2.png
742
1040
media_image2.png
Greyscale
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon et al. (US 20200212117 A1), hereinafter referred to as "Jeon".
Regarding claim 1, Jeon discloses a display apparatus, comprising: a substrate that includes a pixel (110 in Jeon figure 3); a light-emitting diode in the pixel (140 in Jeon figure 3); a first insulating layer around the light-emitting diode (114 in Jeon figure 3; it is on left and right of 140 and is thus around it); a second insulating layer on the first insulating layer (115 in Jeon figure 3); and a first bank around the second insulating layer (116 in Jeon figure 3; it is in close proximity to and is thus around the second insulating layer).
Regarding claim 7, Jeon discloses all of the limitations of claim 1, and further discloses that a first vertical level of a top surface of the first bank is lower than a second vertical level of a top surface of the light-emitting diode (top surface of 116 is below top surface of 140 in Jeon figure 3).
PNG
media_image3.png
484
839
media_image3.png
Greyscale
PNG
media_image4.png
481
824
media_image4.png
Greyscale
Claims 1, 13, 15, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US 20230307426 A1), hereinafter referred to as “Liu”.
Regarding claim 1, Liu discloses A display apparatus, comprising: a substrate that includes a pixel (100 in Liu figure 16); a light-emitting diode in the pixel (300 in figure 16); a first insulating layer around the light-emitting diode (114 labeled in Liu figure 2); a second insulating layer on the first insulating layer (115 labeled in Liu figure 2); and a first bank around the second insulating layer (520 in Liu figure 16; it is in close proximity to and thus is around the second insulating layer).
Regarding claim 13, Liu discloses all of the limitations of claim 1, and further discloses a second bank on the first insulating layer (510 in figure 16), and the second bank is on a portion of a side surface of the light-emitting diode (510 is on portions of the left side and the right sides in figure 16).
Regarding claim 15, Liu discloses all of the limitations of claim 13, and further discloses that an upper end of the second bank is between an end of an upper surface of the light-emitting diode and an end of a lower surface of the light-emitting diode (top surface of second bank 510 is between the upper surface and lower surface of diode 300).
Regarding claim 16, Liu discloses all of the limitations of claim 13, and further discloses that a first spacing between an upper end of the second bank and an end of an upper surface of the light-emitting diode is smaller than a second spacing between the upper end of the second bank and an end of a lower surface of the light-emitting diode (top of 510 is closer to the top of the diode than the bottom of the diode 300 in figure 16, so the spacing between the top of the bank and the top of the diode is smaller).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
