DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 30 March 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-13, and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Okubo et al. (US 2012/0290769) in view of Bae et al. (US 2024/0069782).
In regards to claim 1, Okubo teaches a memory system (flash memory device 1, figure 1) comprising:
a first memory that is non-volatile (flash memory 4, figure 1); and
a controller (memory controller 3, figure 1) that has a host interface (external interface 2, figure 1) and a second memory, and is configured to control the first memory (paragraph 0072), wherein the controller is configured to:
in response to a write command received from a host device (Yes arrow of S101 leads to step S103, figure 14), determine whether a region designation command, which requests securing of a designated region having consecutive physical addresses in a storage region of the first memory and specifies consecutive logical addresses to be mapped to consecutive physical addresses and a data size, has been also received from the host device in association with the write command (“in step S702, it is determined whether or not a logical block exists in the sequential writing block management table 77”, paragraph 0337; “Here, in a case where the sequential writing start command from the host device 5 side is received”, paragraph 0340; “In the sequential writing start command, as shown in FIG. 26, the logical address serving as the writing start address of data for the object of sequential writing, and the size (total size) of the data that is desired to be sequentially written are designated together.”, paragraph 0297);
in response to determining that the region designation command has been received from the host device in association with the write command, secure the designated region having the consecutive physical addresses in the storage region of the first memory, write data corresponding to the consecutive logical addresses in the consecutive physical addresses in the designated region, respectively, and store a first address conversion information in which a head physical address of the consecutive physical addresses is associated with a head logical address of the consecutive logical addresses and the data size (“Here, in a case where the sequential writing start command from the host device 5 side is received, the sequential writing block 50 is typically assigned to the relevant logical block in consequence of the process of FIG. 27 earlier. As a result, sequential writing is performed to the assigned sequential writing block 50 in step S703. After the execution of the sequential writing in step S703, in step S704, a process for registering the final writing physical page address in the sequential writing block 77 is performed.”, paragraphs 0340-0341);
in response to determining that the region designation command has not been received from the host device with the write command (“When, in step S702, a negative result is obtained because a logical block does not exist in the sequential writing block management table 77, the process shifts to a process for page level writing shown in FIG. 21.”, paragraph 0338), write data to a predetermined region out of the designated region in the storage region of the first memory (“When, in step S401, an affirmative result is obtained because the logical block exists in the page-level management table 75, the process proceeds to step S406 as shown in FIG. 21, where writing to the page-level management block 40 is performed. That is, data having a writable size within the data received from the host device 5 side is written to the page-level management block 40 that has been assigned to the logical block address for the object of the relevant writing-in-logical-block process in the page-level management table 75.”, paragraph 0262), and store a second address conversion information in which a physical address of the predetermined region and logical addresses assigned to the write command are associated with each other (“Then, after the execution of the writing in step S406, in step S407, the update of the page-level map 76 is performed. That is, the value of the page-level map 76 corresponding to the data that has been received from the host device 5 side and written is updated.”, paragraph 0280); and
in response to a first read command, which is received from the host device and has a logical address assigned thereto that correspond to data stored in the designated region, determine a physical address corresponding to the logical address assigned to the first read command, using the first address conversion information (“Here, when data of the flash memory 4 is to be read, the host device 5 sends to the memory controller 3, as a read command, a command that specifies the beginning logical address (specified by at least a set of a logical block address and a logical page address) at which reading data exists, and the data size. In response to this, the memory controller 3 reads data at a specified size from the specified logical address, and sends this data to the host device 5.”, paragraph 0075; “As shown in FIG. 11, the sequential writing block management table 77 is information in which physical block addresses and final writing logical page addresses are associated with logical block addresses.”, paragraph 0149).
Okubo fails to teach that the first address conversion information and the second address conversion information are stored in the second memory. Bae teaches that the first address conversion information and the second address conversion information are stored in the second memory (“The memory controller 120 may load and use a portion of the zone map table of the logical units LU allocated to the zone write ZW and the page map table PM of the logical units LU allocated to the zone write ZW and the logical units LU allocated to the random write RW to the internal buffer 123.”, paragraph 0147). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Okubo with Bae such that the first address conversion information and the second address conversion information are stored in the second memory in order to shorten access latency to the address conversion information.
In regards to claim 2, Okubo further teaches that the controller is further configured to determine the physical address based on a physical address offset from the head physical address specified in the first address conversion information, wherein the physical address offset is equal to an offset of the logical address assigned to the first read command from the head logical address specified in the first address conversion information (“Furthermore, in the sequential writing management block 50, similarly to the case of the block-level management block 30 shown in FIG. 4, the value of the logical page address 57 matches the physical page address of the physical page in which the data of the relevant logical page address 57 has been written (in FIG. 6, the value i of the physical page address at which the additional information 52 has been stored matches the value i of the logical page address 57 that has been stored in the relevant additional information 52.”, paragraph 0116).
In regards to claim 3, Bae further teaches that a logical-to-physical address conversion table is also stored in the storage region of the first memory (“For example, the memory controller 120 may write (or back up) the page map table of the target zone in (or to) the meta area MA of the nonvolatile memory device 110.”, paragraph 0291), and the logical-to-physical address conversion table contains a plurality of mappings of logical addresses to physical addresses in a one-to-one manner (“The memory controller 120 may map the zones to the erase units using a zone map table and may map logical addresses to pages using a page map table.”, paragraph 0140), and
the controller, in response to a second read command, which is received from the host device and has a logical address assigned thereto (“Referring to FIGS. 1, 27, and 28, in operation S1710, the memory controller 120 may receive a read request RD from the external host device.”, paragraph 0303) that correspond to data stored outside the designated region (“When the zone map service of the target zone is not activated”, paragraph 0305), is further configured to read the logical-to-physical address conversion table from the first memory (“When the free space is present in the meta buffer MB or when the free space is secured by discarding the page map table selected as the victim data, in operation S1760, the memory controller 120 may read a page map table corresponding to the logical address included in the read request RD from the meta area MA of the nonvolatile memory device 110.”, paragraph 0307) and refers to the read logical-to-physical address conversion table to determine a physical address corresponding to the logical address assigned to the second read command (“Afterwards, the memory controller 120 may perform the read operation by performing operation S1780 and operation S1790 based on the logical address and the partial page map table pPM.”, paragraph 0307; “For example, the memory controller 120 may identify the target zone based on the logical address included in the read request RD and the zone map table ZM, may calculate the offset of the write pointer WP from the logical address, and may calculate the physical address of the nonvolatile memory device 110 based on the offset. The memory controller 120 may read the data from the nonvolatile memory device 110 using the calculated physical address”, paragraph 0304).
In regards to claim 7, Okubo further teaches that the controller, in response to the region designation command received from the host device (“Then, in a case where the sequential writing start command is received, the process proceeds to step S502.”, paragraph 0315) along with consecutive logical addresses of data already written in the first memory, is further configured to not rewrite the data already written in the first memory, when the data already written in the first memory are stored in consecutive physical addresses of the storage region (“When, in step S502, an affirmative result is obtained because a logical block exists in the sequential writing block management table 77, the processing shown in FIG. 27 is completed.”, paragraph 0317).
In regards to claim 8, Bae further teaches that the controller, in response to a designated region check command received from the host device (“Referring to FIGS. 1, 3A to 3E, and 13, in operation S610, the memory controller 120 of the storage device 100 may receive the open zone request OZ or the write request WR from the external host device.”, paragraph 0216) along with the consecutive logical addresses (“Because the external host device writes the data based on the sequential logical addresses within the zone, the storage device 100 may write the data corresponding to the sequential logical addresses at pages corresponding to sequential physical addresses.”, paragraph 0133), is further configured to check a state of an address conversion information related to the consecutive logical addresses (“In response to the open zone request OZ or the write request WR causing the opening of the new zone, in operation S620, the memory controller 120 may determine whether the number of free erase units EU is greater than a fourth threshold value TH4.”, paragraph 0217) and transmits a determination result to the host device (“In operation S650, the memory controller 120 may transmit a response including information about the available zone type to the external host device.”, paragraph 0219), and
the designated region check command is received from the host device (“Referring to FIGS. 1, 3A to 3E, and 13, in operation S610, the memory controller 120 of the storage device 100 may receive the open zone request OZ or the write request WR from the external host device.”, paragraph 0216) before the region designation command is received from the host device along with the consecutive logical addresses (“In operation S660, the memory controller 120 may receive a request for selecting a zone type from the external host device. The request for selecting the zone type may include information about a type of a zone which the external host device desires to open, from among the first-type zone and the second-type zone.”, paragraph 0220).
Okubo further teaches that the consecutive logical addresses are of data already written in the first memory (“When, in step S502, an affirmative result is obtained because a logical block exists in the sequential writing block management table 77, the processing shown in FIG. 27 is completed.”, paragraph 0317).
In regards to claim 9, Bae further teaches that the designated region check command is received from the host device (“Referring to FIGS. 1, 3A to 3E, and 13, in operation S610, the memory controller 120 of the storage device 100 may receive the open zone request OZ or the write request WR from the external host device.”, paragraph 0216) before a read command to which a logical address included in the consecutive logical addresses of data already written in the first memory is assigned, is received from the host device (“Referring to FIGS. 1, 27, and 28, in operation S1710, the memory controller 120 may receive a read request RD from the external host device.”, paragraph 0303).
In regards to claim 10, Bae further teaches that the consecutive logical addresses assigned to the region designation command specify data having a rewrite frequency equal to or less than a predetermined value (“For example, when the frequency of update of the data of the first zone Z1 is lower than a first threshold value, the memory controller 120 may classify the first zone Z1 as a cold zone.”, paragraph 0382).
In regards to claim 11, Bae further teaches that the controller, in response to the region designation command received from the host device (“Referring to FIGS. 1 and 5, in operation S110, the memory controller 120 of the storage device 100 may receive an open zone request OZ from the external host device.”, paragraph 0169) along with a logical address (“Because the external host device writes the data based on the sequential logical addresses within the zone, the storage device 100 may write the data corresponding to the sequential logical addresses at pages corresponding to sequential physical addresses.”, paragraph 0133), is further configured to determine a physical address corresponding to the logical address and store in the second memory, a second address conversion information in which the corresponding physical address is associated with the logical address and the data size of the data corresponding to the logical address (“The memory controller 120 may map the zones to the erase units using a zone map table and may map logical addresses to pages using a page map table.”, paragraph 0140; “The memory controller 120 may load and use a portion of the zone map table of the logical units LU allocated to the zone write ZW and the page map table PM of the logical units LU allocated to the zone write ZW and the logical units LU allocated to the random write RW to the internal buffer 123.”, paragraph 0147).
Okubo further teaches that the logical address is of data already written in the first memory (“When, in step S502, an affirmative result is obtained because a logical block exists in the sequential writing block management table 77, the processing shown in FIG. 27 is completed.”, paragraph 0317).
In regards to claim 12, Bae further teaches that the data size of the data corresponding to the logical address is of a predetermined logical unit size (“The number of zones capable of being allocated to the logical unit LU allocated to the zone write ZW and the size of each of the zones may be determined by the external host device or the storage device 100. Each zone may include at least one erase unit or two or more erase units.”, paragraph 0139).
In regards to claim 13, Bae further teaches that the logical address assigned to the region designation command specify data having a required access speed equal to or more than a predetermined value (“Unlike the zone, another zone for storing data requiring a fast speed or important data may be set to a cell type lower than the highest cell type that the storage device 100 supports.”, paragraph 0188).
In regards to claim 21, Bae further teaches that the first address conversion information is stored in a first address conversion table having a total data size that is smaller than a size of the second memory (“Referring to FIGS. 1, 16, and 17, the internal buffer 123 may include a meta buffer MB, a read buffer RB, and a zone buffer ZB. The meta buffer MB may be used to store the meta data. For example, the meta buffer MB may store a zone map table ZM and the page map table PM.”, paragraph 0255), and the second address conversion information is stored in a second address conversion table having a total size that is larger than the size of the second memory (“Because the storage capacity of the internal buffer 123 is limited, it may be impossible to load all the data of the meta area MA of the nonvolatile memory device 110 to the meta buffer MB. The memory controller 120 may allow the zone map table ZM to reside in the meta buffer MB and may load a necessary or desired portion of the page map tables PM_Z1, PM_Z2, PM_Z3, PM_Z4, PM_Z5, PM_Z6, PM_Z7, and PM_Z8 to the meta buffer MB as the partial page map table pPM.”, paragraph 0302).
In regards to claim 22, Bae further teaches that the first address conversion table is stored entirely in the second memory and the second address conversion table is stored partially in the second memory (“Because the storage capacity of the internal buffer 123 is limited, it may be impossible to load all the data of the meta area MA of the nonvolatile memory device 110 to the meta buffer MB. The memory controller 120 may allow the zone map table ZM to reside in the meta buffer MB and may load a necessary or desired portion of the page map tables PM_Z1, PM_Z2, PM_Z3, PM_Z4, PM_Z5, PM_Z6, PM_Z7, and PM_Z8 to the meta buffer MB as the partial page map table pPM.”, paragraph 0302).
In regards to claim 23, Okubo further teaches that the region designation command provides no instruction to write data into the first memory (Figure 27 shows the process of performing the sequential writing start command. The only actions performed are garbage collection if there is no vacancy and registering in the sequential writing block management table. Figure 26 shows that the sequential writing start command has a size of the logical block size. Then there are four write commands, each of which write a quarter of a logical block size, starting from the same logical address.).
In regards to claim 24, Okubo further teaches that in the first address conversion information, no other physical address than the head physical address is associated with any logical address (See block-level management table 70 in figure 8), and
in the second address conversion information, the physical addresses of the predetermined region and the logical addresses assigned to the write command are associated with each other for each page, which is a unit data size of data writing into the first memory (See page-level map 76 in figure 10).
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Okubo et al. (US 2012/0290769) in view of Bae et al. (US 2024/0069782) and Kanno (US 2021/0255803).
In regards to claim 4, Okubo further teaches that the controller, in response to the region designation command received from the host device along with consecutive logical addresses, is further configured to store a third address conversion information in which a head of the new physical addresses is associated with a head of the consecutive logical addresses (“The block registration process of step S603 is the same as the block registration process of step S214 earlier.”, paragraph 0329; See paragraph 0254).
Okubo in view of Bae fails to teach that the controller, in response to the region designation command received from the host device along with consecutive logical addresses of data already written in the first memory, is further configured to rewrite data already written in the first memory at new physical addresses that are consecutive in the storage region.
Kanno teaches that the controller, in response to the region designation command received from the host device along with consecutive logical addresses of data already written in the first memory, is further configured to rewrite data already written in the first memory at new physical addresses that are consecutive in the storage region (“When receiving from the host 2 the write request for rewriting the data into the zone #1 which is in the closed state, the controller 4 re-opens the zone #1 (QLC block #1). Then, the controller 4 reads the above-described remaining write data stored in the shared QLC buffer 201, from the shared QLC buffer 201, and transfers the remaining write data to the internal buffer 161. The remaining write data transferred from the shared QLC buffer 201 to the internal buffer 161 are written into the QLC block #1 at the timing at which the write data become writable into the QLC block #1.”, paragraph 0165).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Okubo with Bae and Kanno such that the controller, in response to the region designation command received from the host device along with consecutive logical addresses of data already written in the first memory, is further configured to rewrite data already written in the first memory at new physical addresses that are consecutive in the storage region in order to more efficiently use memory space.
In regards to claim 5, Bae further teaches that the controller, in response to a designated region check command received from the host device along with the consecutive logical addresses (“Referring to FIGS. 1, 3A to 3E, and 13, in operation S610, the memory controller 120 of the storage device 100 may receive the open zone request OZ or the write request WR from the external host device.”, paragraph 0216), is further configured to check a state of an address conversion information related to the consecutive logical addresses (“In response to the open zone request OZ or the write request WR causing the opening of the new zone, in operation S620, the memory controller 120 may determine whether the number of free erase units EU is greater than a fourth threshold value TH4.”, paragraph 0217) and transmit a determination result to the host device (“In operation S650, the memory controller 120 may transmit a response including information about the available zone type to the external host device.”, paragraph 0219), and
the designated region check command is received from the host device (“Referring to FIGS. 1, 3A to 3E, and 13, in operation S610, the memory controller 120 of the storage device 100 may receive the open zone request OZ or the write request WR from the external host device.”, paragraph 0216) before the region designation command is received from the host device along with the consecutive logical addresses (“In operation S660, the memory controller 120 may receive a request for selecting a zone type from the external host device. The request for selecting the zone type may include information about a type of a zone which the external host device desires to open, from among the first-type zone and the second-type zone.”, paragraph 0220).
Kanno further teaches the consecutive logical addresses are of data already written in the first memory (“When receiving from the host 2 the write request for rewriting the data into the zone #1 which is in the closed state, the controller 4 re-opens the zone #1 (QLC block #1). Then, the controller 4 reads the above-described remaining write data stored in the shared QLC buffer 201, from the shared QLC buffer 201, and transfers the remaining write data to the internal buffer 161.”, paragraph 0165).
In regards to claim 6, Bae further teaches that the designated region check command is received from the host device command (“Referring to FIGS. 1, 3A to 3E, and 13, in operation S610, the memory controller 120 of the storage device 100 may receive the open zone request OZ or the write request WR from the external host device.”, paragraph 0216) before a read command to which a logical address included in the consecutive logical addresses of data already written in the first memory is assigned, is received from the host device (“Referring to FIGS. 1, 27, and 28, in operation S1710, the memory controller 120 may receive a read request RD from the external host device.”, paragraph 0303).
Response to Arguments
Applicant’s arguments, see page 8, filed 30 March 2026, with respect to the 112(b) rejection have been fully considered and are persuasive. The 112(b) rejection has been withdrawn.
Applicant's arguments, see pages 8-9, filed 30 March 2026, with respect to the obviousness rejection have been fully considered but they are not persuasive.
Applicant argues that Okubo’s sequential writing start command is a write command itself. However, the Examiner disagrees. Figure 27 shows the execution of the sequential writing start command. The only actions that occur are garbage collection if there is no vacancy and registering in the sequentially written block management table. Contrast this to figure 29, which shows the execution of a write command. Step S703 shows the actual writing. The proper interpretation of the sequential writing start command is reinforced by figure 26. At t1, the sequential writing start command occurs for logical address 0 and for the logical block size. At t2, a write command occurs for logical address 0 and for a quart of the logical block size. If the sequential writing start command was actually a write command, there would be no reason to rewrite the data at logical address 0 at time t1. Figure 26 shows four write commands that cover the entire area specified by the sequential writing start command. This implies that the sequential writing start command is not the write command itself. Additionally, the data is sent at times t3, t5, t7, and t9, immediately following each write command. There is no corresponding data sent for the sequential writing start command. This also implies that the sequential writing start command is not the write command itself. Based on this evidence, the Examiner concludes that the sequential writing start command is not a write command itself but instead is an example of the claimed region designation command.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Porzio et al. (US 2026/0003510) as supported by its provisional application teaches, based on receiving a write command, determine whether the write command is associated with a zone using an open zone command.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 15 June 2026
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