Prosecution Insights
Last updated: October 01, 2026
Application No. 18/820,135

SILICON CARBIDE DIODE WITH REDUCED VOLTAGE DROP, AND MANUFACTURING METHOD THEREOF

Non-Final OA §DP
Filed
Aug 29, 2024
Priority
Jul 27, 2020 — IT 102020000018130 +2 more
Examiner
HARRISON, MONICA D
Art Unit
Tech Center
Assignee
STMicroelectronics N.V.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
883 granted / 962 resolved
+31.8% vs TC avg
Minimal +3% lift
Without
With
+2.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
16 currently pending
Career history
977
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
40.0%
+0.0% vs TC avg
§102
42.4%
+2.4% vs TC avg
§112
5.4%
-34.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 962 resolved cases

Office Action

§DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority This application discloses and claims only subject matter disclosed in prior Application No. 18/334,275, filed 6/13/23, and names the inventor or at least one joint inventor named in the prior application. Accordingly, this application may constitute a continuation or divisional. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 9-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 and 11-16 of U.S. Patent No. 11,715,769 B2 (Rascuna et al). Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed subject matter of claims 9-17 of the instant application may be found in claims 9 and 11-16 of the patent. Regarding claim 9, Rascuna et al 769’ discloses a method for manufacturing an electronic device, comprising: providing a solid body of silicon carbide having a surface and having a first conductivity type; forming in the solid body, by implantation of doping agents having a second conductivity type via a first hard mask, a first implanted region and a second implanted region extending downward from the surface of the solid body; forming in the solid body, by implantation of doping agents having the first conductivity type via a second hard mask, a third doped region laterally delimited by the first implanted region and the second implanted region and extending downward from the surface of the solid body; forming Schottky-contact metal portions on the surface and in direct contact with the surface; and forming ohmic-contact metal portions on the surface and in direct contact with the first and second implanted regions (claim 9). Regarding claim 10, Rascuna et al 769’ discloses wherein the third implanted region includes a plurality of doped sub-regions vertically stacked on each other and each laterally delimited by the first implanted region and the second implanted region and each having a respective conductivity level higher than that of the bulk portion (claim 9). Regarding claim 11, Rascuna et al 769’ discloses wherein the conductivity level of at least one of the doped sub-regions is different from the conductivity level of at least one other of the doped sub-regions (claim 9). Regarding claim 12, Rascuna et al 769’ discloses wherein forming the plurality of doped sub-regions includes: forming a first sub-region in the solid body starting from the surface; forming a second sub-region in the solid body vertically adjacent to the first sub-region; and forming a third sub-region vertically adjacent to the second sub-region (claim 11). Regarding claim 13, Rascuna et al 769’ discloses wherein the second sub-region has a conductivity higher than the first sub-region and the third sub-region (claim 12). Regarding claim 14, Rascuna et al 769’ discloses wherein: forming the first sub-region includes carrying out a first implantation with an energy between 10 keV and 20 keV; and forming the second and third sub-regions includes carrying out a second implantation with an energy between 150 keV and 250 keV (claim 13). Regarding claim 15, Rascuna et al 769’ discloses wherein: forming the first sub-region includes carrying out a first implantation with an implantation dose between 1.0-1011 and 1.0-1013 at/cm2; and forming the second and third sub-regions includes carrying out a second implantation with an implantation dose between 1.0-1013 and 1.0-1015 at/cm2 (claim 14). Regarding claim 16, Rascuna et al 769’ discloses wherein the first, second, and third sub- regions are formed in such a way that a sum of thicknesses of the first, second, and third sub- regions is equal to or less than a thickness, in the direction, of each one of the first and second implanted regions (claim 15). Regarding claim 17, Rascuna et al 769’ discloses wherein material of the solid body is one of: 4H-SiC, 6H-SiC, 3C-SiC, or 15R-SiC (claim 16). Allowable Subject Matter Claims 1-8 and 18-21 are allowed over the prior art. Reasons for Allowance The following is an examiner’s statement of reasons for allowance: The prior art does not disclose nor fairly suggest methods, comprising: forming, on the drift layer, a second hard mask having second windows exposing the drift layer; forming second implanted regions between the first implanted regions by implanting dopants of the first conductivity type via the second windows; and forming Schottky-contact metal portions in direct contact with the first implanted regions; and forming ohmic-contact metal portions in direct contact with the first and second implanted regions (claim 2) and forming first and second ohmic contacts on the surface and extending at least partially into the first and second implanted regions, respectively; forming, via second hard mask, a doped sub-region extending between the first and second implanted regions, the doped sub-region extending into the epitaxial layer from the surface and having the first conductivity type and a conductivity level higher than that of the bulk portion; and forming a first metal layer on the epitaxial layer and on the first and second ohmic contacts, the metal layer in direct contact with the doped sub-region (claim 18) as described in the independent claims and in the context of their recited processes, along with their depending claims. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Mazzola et al (US 2008/0003731 A1) discloses a switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MONICA D HARRISON/Primary Examiner, Art Unit 2815 mdh September 18, 2026
Read full office action

Prosecution Timeline

Aug 29, 2024
Application Filed
Sep 23, 2026
Non-Final Rejection mailed — §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
94%
With Interview (+2.7%)
2y 2m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 962 resolved cases by this examiner. Grant probability derived from career allowance rate.

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