Detailed Action
Status of Claims
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Claims 1-20 are rejected.
This Action is Non-Final.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/30/2024 and 08/29/2025,the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10,16-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over LEE (US Patent Application Pub. No: 20190115937 A1) in view of DU (US Patent Application Pub. No: 20230384945 A1).
As per claim 1,LEE teaches a data conversion circuit [Fig.1, a data conversion circuit.], comprising
a data cache module [Fig.1, a data storage circuit 1001], a selective output module [Fig.1, the memory controller 1002.], and a detection module [Paragraph 0004, The error codes may include an error detection code (EDC) which is capable of detecting errors,…], wherein the data cache module is configured to receive a multi-bit parallel first signal, wherein the first signal comprises a first data signal and a first check code signal [Paragraph 0064, The memory controller 2002 may supply the data, a data strobe signal, a command, an address and a clock signal to the data storage circuit 2003 in response to the request signal, and the data storage circuit 2003 may execute a write operation or a read operation in response to the command.];
the detection module is configured to receive a read command signal, and output a corresponding enable signal according to a signal required to be transmitted currently being the first data signal or the first check code signal [Paragraphs 0004-0005, Whenever data is transmitted in semiconductor devices, error codes which are capable of detecting the occurrence of errors may be generated and transmitted with the data to guarantee the reliability of data transmission. The error codes may include an error detection code (EDC) which is capable of detecting errors and an error correction code (ECC) which is capable of correcting the errors by itself.], wherein the enable signal comprises a first enable signal corresponding to the first data signal or a second enable signal corresponding to the first check code signal [Paragraphs 0024-0025, The error occurrence control circuit 2 may generate the error insertion code EI<3:1> which is counted at a point of time that the column pulse CASP is created while the read signal RD is enabled. The read signal RD may be enabled to perform a read operation. The column pulse CASP may be created whenever the data D<4:1> are outputted from a memory cell array (not illustrated) during the read operation.]; and
the selective output module is coupled to the data cache module and the detection module, and is configured to receive the first signal and selectively output the first data signal or the first check code signal based on the enable signal [Paragraphs 0006;0024, The parity generation circuit may be configured to perform a logical operation of logic levels of at least two selected from bits included in data to generate a parity, in response to an error check matrix. The data conversion circuit may be configured to convert the data to generate internal data, in response to an error insertion code. The parity conversion circuit may be configured to convert the parity to generate an internal parity, in response to the error insertion code.].
LEE does not explicitly disclose selection output module.
Du discloses selection output module is coupled to the data cache module and the detection module [Fig.2; Paragraphs 0073, Each data selection module 10 transmits input/output data of one DQ port to the check module 20. For example, the first data selection module 10 transmits the input/output data of the first DQ port to the check module 20. For example, the second data selection module 10 transmits the input/output data of the second DQ port to the check module 20 .]
It would have been obvious one ordinary skill in the art before the effective filling
date of the claimed invention, to include Du’s data processing circuit into LEE’s electronic device for the benefit of the circuit can take into account the size of the semiconductor memory and the reliability of data read and write (DU,[0049]-[0050]) to obtain the invention as specified in claim 1.
As per claim 2, LEE and DU teach all the limitations of claim 1 above, where LEE teaches, the circuit, wherein the first signal is eighteen-bit data, the first data signal is sixteen-bit data, and the first check code signal is two-bit data [LEE, Paragraphs 0003-0005, Recently, a DDR2 scheme or a DDR3 scheme receiving and outputting four-bit data or eight-bit data during each clock cycle time has been used to improve the operation speeds of semiconductor devices.].
As per claim 3, LEE and DU teach all the limitations of claim 1 above, where LEE and DU teach, the circuit, wherein the detection module comprises a clock counting module and a signal generating module, wherein the clock counting module is configured to reset and count, in response to receiving the read command signal, a number of system clock cycles since receiving the read command signal [LEE, Paragraphs 0006;0024, The parity generation circuit may be configured to perform a logical operation of logic levels of at least two selected from bits included in data to generate a parity, in response to an error check matrix. The data conversion circuit may be configured to convert the data to generate internal data, in response to an error insertion code. The parity conversion circuit may be configured to convert the parity to generate an internal parity, in response to the error insertion code.]; and
the signal generating module is coupled to the clock counting module, and is configured to output the first enable signal in response to the number of system clock cycles counted by the clock counting module does not reach a first threshold, and output the second enable signal in response to the number of system clock cycles counted by the clock counting module reaches the first threshold, wherein the first threshold is set based on a length of the first data signal [DU, Paragraphs 0179-0180, …, if the second clock signal corresponds to the edge trigger, when the trigger level inversion moment of the second clock signal is later than the occurrence moment of the second trigger edge of the first clock signal, and the trigger level inversion moment of the second clock signal is earlier than the occurrence moment of the third trigger edge of the first clock signal, it may be determined that the trigger level inversion moment of the second clock signal is aligned with the appearance moment of the second trigger edge of the first clock signal.].
As per claim 4, LEE and DU teach all the limitations of claim 1 above, where LEE and DU teach, the circuit, wherein there are N selective output modules [LEE, Paragraph 0055, The electronic device according to an embodiment may generate the error insertion code EI<3:1> using an error check matrix and may include errors into the data D<4:1> and the parity P<3:1> to generate the internal data ID<4:1> and the internal parity IP<3:1> according to a logic level combination of the error insertion code EI<3:1>.];
the data cache module is configured to divide the first data signal into N data sub-signals and divide the first check code signal into M check code sub-signals based on bits [LEE, Paragraph 0055, The electronic device according to an embodiment may generate the error insertion code EI<3:1> using an error check matrix and may include errors into the data D<4:1> and the parity P<3:1> to generate the internal data ID<4:1> and the internal parity IP<3:1> according to a logic level combination of the error insertion code EI<3:1>. The electronic device according to an embodiment may generate the syndrome signal S<3:1> in response to the internal data ID<4:1> including an error and the internal parity IP<3:1> including an error and may verify whether an error correction operation is normally performed by the error check matrix according to identity or non-identity of the syndrome signal S<3:1> and the error insertion code EI<3:1>.]; and
the data cache module is further configured to respectively output the data sub-signals and the check code sub-signals to the N selective output modules in a manner of outputting the first signal in parallel, wherein a data volume in each data sub-signal does not exceed a number of the selective output modules; wherein, M and N are positive integer [DU, Abstract, Paragraphs 0007; 0011, …The circuit includes: a data selection module configured to receive and output write data if a received write control command is in a first level state, and receive and output read data if a received read control command is in the first level state; a check module configured to receive the write data or the read data, check the write data or the read data, and obtain write check data or read check data, and output the write check data or the read check data; and a data output module configured to receive the write check data or the read check data, output the write check data if the write control command is in the first level state.].
As per claim 5, LEE and DU teach all the limitations of claim 4 above, where LEE and DU teach, the circuit, wherein sequential logic of a plurality of the selective output modules is configured [DU, Paragraph 0011, The data processing method is applied to the data processing circuit, and includes: receiving and outputting, by a data selection module, write data if a received write control command is in a first level state, and receiving and outputting, by the data selection module, read data if a received read control command is in the first level state;….]; and
the data cache module is configured to output the first signal to corresponding selective output modules according to the sequential logic [LEE, Paragraphs 0006- 0007,…The data conversion circuit may be configured to invert a logic level of at least one of bits included in the data to generate internal data, according to a logic level combination of the error insertion code. The parity conversion circuit may be configured to invert a logic level of at least one of bits included in the parity to generate an internal parity, according to a logic level combination of the error insertion code.].
As per claim 6, LEE and DU teach all the limitations of claim 4 above, where LEE and DU teach, the circuit, wherein the selective output module comprises a check code transmission unit and a data transmission unit, wherein the check code transmission unit is coupled to the data cache module, has a control terminal configured to receive the second enable signal, and is configured to receive the first check code signal and output the first check code signal in response to the second enable signal is valid [LEE, Paragraph 0025, The error occurrence control circuit 2 may generate an error insertion code EI<3:1> in response to a read signal RD and a column pulse CASP. The error occurrence control circuit 2 may generate the error insertion code EI<3:1> which is counted at a point of time that the column pulse CASP is created while the read signal RD is enabled. The read signal RD may be enabled to perform a read operation.] ; and
the data transmission unit is coupled to the data cache module, has a control terminal configured to receive the first enable signal, and is configured to receive the first data signal and output the first data signal in response to the first enable signal is valid [DU, Paragraph 0052;0063,…The error occurrence control circuit 2 may generate an error insertion code EI<3:1> in response to a read signal RD and a column pulse CASP. The error occurrence control circuit 2 may generate the error insertion code EI<3:1> which is counted at a point of time that the column pulse CASP is created while the read signal RD is enabled. The read signal RD may be enabled to perform a read operation. The column pulse CASP may be created whenever the data D<4:1> are outputted from a memory cell array (not illustrated) during the read operation. A configuration and an operation of the error occurrence control circuit 2 will be described with reference to FIGS. 4 and 5 later.].
As per claim 7, LEE and DU teach all the limitations of claim 6 above, where DU teaches, the circuit, wherein the check code transmission unit comprises a first transmission gate, wherein the first transmission gate has a control terminal configured to receive the second enable signal, and is turned on to output the first check code signal in response to the second enable signal is valid [DU, Paragraph 0052;0063,…The error occurrence control circuit 2 may generate an error insertion code EI<3:1> in response to a read signal RD and a column pulse CASP. The error occurrence control circuit 2 may generate the error insertion code EI<3:1> which is counted at a point of time that the column pulse CASP is created while the read signal RD is enabled. The read signal RD may be enabled to perform a read operation.].
As per claim 8, LEE and DU teach all the limitations of claim 6 above, where DU teaches, the circuit, wherein the data transmission unit comprises a first flip-flop and a second transmission gate, wherein the first flip-flop has a data terminal configured to receive the first data signal, a clock terminal configured to receive a system clock signal, and an output terminal coupled to an input terminal of the second transmission gate [DU, Paragraphs 0183; 0195, …, the first transmission data and the second transmission data transmitted in parallel may be generated through the data processing unit 414. Since the (i+n)-th bit of the first transmission data is transmitted at the second trigger edge of the first clock signal, and the i-th bit of the second transmission data is transmitted at the second trigger edge of the first clock signal, the sequence adjustment unit 415 may simultaneously receive the i-th bit and the (i+n)-th bit transmitted in parallel. The i-th bit and the (i+n)-th bit can be flexibly adjusted by adjusting the output ports of the i-th bit and the (i+n)-th bit that are transmitted in parallel, thereby improving the transmission accuracy of the write data and the read data.]; and
the second transmission gate has a control terminal configured to receive the first enable signal, and is turned on to output the first data signal in response to the first enable signal is valid [DU, Paragraphs 0183; 0195,Moreover, for the second D flip-flop D2, since there is a certain transmission delay between the first D flip-flop D1 and the second D flip-flop D2, if the first clock signal CLK1 is at the second trigger edge, the data of the port D of the second D flip-flop D2 is still the i-th bit, and at this time, the i-th bit may be transmitted to the output terminal Q of the second D flip-flop D2; and, if the first clock signal CLK1 is at the third trigger edge, the data of the port D of the second D flip-flop D2 is still the (i+n)-th bit, and at this time, the (i+n)-th bit may be transmitted to the output terminal Q of the second D flip-flop D2.].
As per claim 9, LEE and DU teach all the limitations of claim 6 above, where DU teaches, the circuit, wherein the selective output module further comprises: a cache unit, coupled to the check code transmission unit and the data transmission unit, and is configured to cache and output a signal received currently [DU, Paragraph 0052;0063,…The error occurrence control circuit 2 may generate an error insertion code EI<3:1> in response to a read signal RD and a column pulse CASP. The error occurrence control circuit 2 may generate the error insertion code EI<3:1> which is counted at a point of time that the column pulse CASP is created while the read signal RD is enabled. The read signal RD may be enabled to perform a read operation.].
As per claim 10, LEE and DU teach all the limitations of claim 6 above, where DU teaches, the circuit, wherein the first signal is 36-bit data, the first data signal is 32-bit data, and the first check code signal is four-bit data [DU, Paragraphs 0164-0165, The first output terminal 412 and the second output terminal 413 of the i-th sequence adjustment sub-module 41 are respectively connected to the check module 20. The first output terminal 412 and the second output terminal 413 may be respectively configured to output, to the check module 20, the i-th bit adjusted to the correct transmission sequence and the (i+n)-th bit adjusted to the correct transmission sequence. In one embodiment, the first output terminal 412 is configured to output the i-th bit, and the second output terminal 413 is configured to output the (i+n)-th bit.].
As per claim 16, LEE and DU teach all the limitations of claim 1 above, where DU teaches, wherein there are four selective output modules [DU, Paragraphs 0007;0011,… The data processing circuit includes: [0008] a data selection module configured to receive and output write data if a received write control command is in a first level state, and receive and output read data if a received read control command is in the first level state;…].
As per claim 17, LEE and DU teach all the limitations of claim 1 above, where LEE teaches, wherein the data cache module comprises a first-in first-out data cache, wherein the first-in first-out data cache comprises a data input terminal, an input clock signal terminal, and an output clock signal terminal [LEE, Paragraphs 0064-0065, The memory controller 2002 may supply the data, a data strobe signal, a command, an address and a clock signal to the data storage circuit 2003 in response to the request signal, and the data storage circuit 2003 may execute a write operation or a read operation in response to the command.].
As per claim 20, claim 20 is rejected in accordance to the same rational and reasoning as the above claim 1, wherein claim 20 is the device claim for the system of claim 1.
Allowable Subject Matter
8. Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest “ The circuit …, wherein the first data signal comprises a first group of N data sub-signals and a second group of N data sub-signals, the first check code signal comprises a first group of check code sub-signals and a second group of check code sub-signals, the first enable signal comprises a first enable sub-signal and a second enable sub-signal;
the detection module further comprises: an identification module, configured to receive the read command signal and two initial clock signals, output corresponding enable sub-signal according to one of the initial clock signals which firstly triggering the read command signal, and shield to another of the initial clock signals and output the corresponding enable sub-signal, wherein the two initial clock signals comprise a first initial clock signal and a second initial clock signal having a same frequency and opposite phases; and
the data transmission unit comprises a first data transmission unit and a second data transmission unit, wherein the first data transmission unit has a control terminal configured to receive the first enable sub-signal corresponding to the first initial clock signal, and is configured to receive the first group of N data sub-signals and output the first group of N data sub-signals in response to the first enable sub-signal is valid; and
the second data transmission unit has a control terminal configured to receive the second enable sub-signal corresponding to the second initial clock signal, and is configured to receive the second group of N data sub-signals and output the second group of N data sub-signals in response to the second enable sub-signal is valid.” as recited in claim 11.
9. Dependent claims 12-15 and 18 are allowable as being dependent upon an allowable claim 11.
Conclusion
Choi et al. (US Patent No: 12,361,986 B2) teaches a semiconductor device may include a page buffer comprising first to fifth latches, wherein the first to third latches and the fifth latch are configured to store 4-bit original data, among 5-bit original data, respectively, and the fourth latch is configured to store data identical with the data that has been stored in the second latch and a control circuit configured to determine a program inhibition pattern based on data that have been stored in two of the first to fifth latches and control the page buffer so that data that has been stored in at least one of the first to fifth latches is inverted based on the program inhibition pattern.
CHENG (US Patent Application Pub. No: 20250095712 A1) teaches provides an information transmission method, a memory, a control apparatus. CHENG discloses receiving a first target command sent from the outside; and outputting first duty cycle data of an internal data clock signal through a first group of data ports based on the first target command, where the first duty cycle data persists at the first group of data ports at least until a first stop command sent from the outside is received.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GETENTE A YIMER whose telephone number is (571)270-7106. The examiner can normally be reached on Monday-Friday 6:30-3:00.If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS ALROBAYE can be reached on 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GETENTE A YIMER/Primary Examiner, Art Unit 2181