DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to Applicant’s request for reconsideration filed 3/30/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/30/2026 was filed after the mailing date of the non-final rejection on 12/29/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-9, 11-17 and 19-23 of U.S. Patent No. 12,079,490. Although the claims at issue are not identical, they are not patentably distinct from each other because all the claimed limitations are transparently found in U.S. Patent No. 12,079,490 with obvious wording variations. Take an example to compare claim 1 of pending Application with claim 1 of U.S. Patent No. 12,079,490 as shown below:
Pending Application 18/820,442
U.S. Patent No. 12,079,490
1. A method for operating a memory interface, the method comprising: receiving a signal indicative of a change in operating frequency; and responsive to the signal, updating at least one control and state register (CSR) of at least one respective transceiver of the memory interface through a dedicated bus for transmissions to and receptions from memory.
1. A method for frequency transitioning in a memory interface system, comprising: receiving a signal indicative of a change in operating frequency, to a new frequency, in a processing unit interfacing with memory via the system; switching the system from a normal mode of operation to a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a dedicated bus for transmissions to and receptions from memory used during the normal mode of operation; and operating the system in the new frequency.
As shown in table above, claim 1 of U.S. Patent No. 12,079,490 is comprehensive in scope, which covers all the claimed limitations as shown in underlined portion. Although claim 1 of U.S. Patent No. 12,079,490 does not explicitly disclose responsive to the signal, claim 1 of U.S. Patent No. 12,079,490 discloses received signal to change to a new frequency for switching the system from a normal mode of operation to a transition mode of operation, and then updating control and state register (CSR) banks. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize that the pending Application and U.S. Patent No. 12,079,490 are similar in scope and they are not patentably distinct from each other.
For the same reasons as stated above, claims 3-9, 11-17 and 19-23 of U.S. Patent No. 12,079,490 cover the claimed limitations of 2-20 of pending Application, respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 8-9 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Cox et al. (US 2018/0348838 A1 hereinafter Cox) in view of Searles et al. (US 2013/0124806 A1 hereinafter Seales).
Regarding claim 1, Cox discloses a method for operating a memory interface as shown in figure 10, the method comprising: receiving a signal indicative of a change in operating frequency ([0071], an FSP CONFIG command may be received from command logic); and responsive to the signal, updating at least one mode register of at least one respective transceiver of the memory interface through a dedicated bus for transmissions to and receptions from memory ([0075], update bits of the FSP switch status field of the mode register in the example format of FSP configuration register to indicate that the FSP switch is complete). Cox differs from the claimed invention in not specifically teaching the step of updating at least one control and state register (CSR) of at least one respective transceiver of the memory interface through a dedicated bus for transmissions to and receptions from memory. However, Seales teaches a PHY interface including a clock source and a command and status register ([0016]), wherein the PHY interface is programmed by issuing commands in the command and status register via configuration bus to allow read/write access command and status register ([0007] and [0026]-[0027]), such that control and state register (CSR) banks of respective transceivers of the system is updated through a mission bus used during the normal mode of operation in order to rapidly adjust memory performance level ([0004] and [0046]-[0047]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cox in having the step of updating at least one control and state register (CSR) of at least one respective transceiver of the memory interface through a dedicated bus for transmissions to and receptions from memory, as per teaching of Seales, in order to rapidly adjust memory performance level.
Regarding claim 2, Cox teaches updating the at least one CSR comprises: writing operating parameters to respective CSRs of the at least one CSR ([0022]-[0024], access CSR via uni-directional configuration bus) in order to facility low latency switching between power states.
Regarding claim 8, the limitations are rejected as the same reasons as set forth in claim 1.
Regarding claim 9, the limitations are rejected as the same reasons as set forth in claim 2.
Regarding claim 15, the limitations are rejected as the same reasons as set forth in claim 1.
Regarding claim 16, the limitations are rejected as the same reasons as set forth in claim 2.
Allowable Subject Matter
Claims 3-7, 10-14 and 17-20 would be allowable if rewritten to overcome the rejection(s) under double patenting rejection, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 3/30/2026 have been fully considered but they are not persuasive.
In response to applicant's argument that Searles does not teach "...updating ... through a dedicated bus for transmissions to and receptions from memory..." as in claim 1 because configuration bus 80 of Searles is not "...a dedicated bus for transmissions to and receptions from memory..." as in the amended claim 1, and that CSR 42 of Searles are not configured via any other bus in Searles, Examiner respectfully disagrees. First, claim 1 had never been amended. Second, Applicants fails to provide a sufficient reason on why the configuration bus of Searles is not a dedicated bus and the claim does not explicitly define a dedicated bus. Third, Searles teaches that Phy interface is accomplished by issuing commands or programming specific fields in CSRs via the configuration bus 80, i.e., changing from one PhyPS to another may be accomplished with a single command issued to the DDR Phy interface indirect register space, programming of PhyPS context sensitive CSRs may be accomplished by setting the appropriate PhyPS context and then performing normal indirect CSR writes or reads ([0026]) and trained values are already written to the Phy interface PhyPS[0] CSRs as part of the training ([0046]). Thus, Searles teaches to update at least one control and state register (CSR) of at least one respective transceiver of the memory interface through a configuration bus. Therefore, the combination of Cox and Searles teaches the broad claimed limitations. Accordingly, Examiner respectfully submits that claims 1-2, 8-9, and 15-16 are rejected under the cited references and respectfully requests that the 35 U.S.C. §103 rejection be maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zwerg et al. (US 2017/0185139 A1) discloses a computing device apparatus facilitating to use of a deep low power mode that includes a dedicated bus separate from a system bus connects the non-volatile logic array(s) to the configuration registers and memory, the dedicated bus allows direct connection to the configuration registers and memory to operate under the control of the NVL subsystem (abstract and [0014]-[0016]).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHUO H LI whose telephone number is (571)272-4183. The examiner can normally be reached Mon. Tue. and Thurs. 8:00-4:00 PM.
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/ZHUO H LI/Primary Examiner, Art Unit 2133
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