DETAILED ACTION
This Office Action is in response to the communication filed on 8/30/2024.
Claims 1-20 are pending.
Claims 1-20 are rejected.
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 24 and 25 are objected because “pre-characterized noise level” appears to be a statement regarding a physical law of nature. Examiner believes that Applicant intends this to be an improvement related to data privacy but the phrase is not incorporated into any other security featured, examiner suggests incorporating and using the “pre-characterized noise level” in subsequent limitation in order to better clarify the scope of the claims.
Examiner suggests clarifying whether the (1) pre-characterized noise level, (2) injected noise, (3) random noise are the same noises, different noises and/or levels of noise including how the level of noise related to the injected and/or random noise. Additionally, in order to better clarify the scope of the claims, examiner suggests clarifying what “pre-characterization” means, for example is “pre-characterization” something that is calculated in advance or predictable results produced from a known mathematical relationship?
Claims 2, 19 and 20 are objected to because the term “inject” is very broad, for example is “injecting” something that is transmitted from a separate device or something that is generated as a result of lowering the voltage? Additionally , it is not clear how the “injected noise” provides a security improvement.
Regarding “Low/High reliability storage cells” it is not clear what exactly makes them low or highly reliable (other than being 6t and 8t).
Claim 14 recites limitations previously recited in claim 2.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 18 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 7 and 18 recites the limitation "the four MSD/LSBs of a byte". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-4, 6, 8-9, 12-13, 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Rad (U.S. 20180165466), in view of Hekmatshoartabari (U.S. 20200364032).
Regarding claim 1,
Rad discloses: A method for data manipulation comprising:
accessing data for storage, wherein the data requires differential privacy data manipulation;
preparing the data for storage, wherein the preparing comprises key-based shuffling; (Rad [0035-0038] The client application can secure the image using an encryption key before storage in the cloud server [0006, 0066-0067] teaches that the shuffling can be performed by the client; [0006-0012, 0065-0067, 0075-0080] teaches that the shuffling can be based on a key)
storing the data that was shuffled in a static random-access memory (SRAM), (from the cloud0038]; [0006, 0065-0067] The client application can secure the image using an encryption key (key-based shuffling) before storing (the shuffled data) in the memory of the cloud server; [0135, 0141] teaches that the memory can be SRAM)
performing a read of the data that was stored; and (Rad [0004, 0011, 0043-0044] teaches retrieval of encrypted data (which was previously stored))
unshuffling the data that was read, using key-based unshuffling. (Rad [0004, 0011, 0043-0044] teaches retrieval of encrypted data (which was previously stored); [0006-0012, 0065-0067, 0075-0080] teaches the client decrypting/unshuffling the encrypted/shuffled data which was read form storage)
Rad does not explicitly disclose: wherein the SRAM comprises high-reliability storage cells and low-reliability storage cells;
lowering a supply voltage of the SRAM, wherein the lowering a supply voltage produces a pre-characterized noise level in the SRAM storage cells;
However, in the same field of endeavor Hekmatshoartabari discloses: wherein the SRAM comprises high-reliability storage cells and low-reliability storage cells; (Hekmatshoartabari [0006-0010, 0036-0039, 0067-0070, 0074-0084] teaches a hybrid system that has a computing unit and a noise amplification unit… standard transistors are used in the computing unit whereas transistors with near-zero V.sub.t are used in the noise amplification unit… noise generated by the amplifier circuit is used to generate a stream of random numbers)
lowering a supply voltage of the SRAM, wherein the lowering a supply voltage produces a pre-characterized noise level in the SRAM storage cells; (Hekmatshoartabari [Fig. 18, 0006-0010, 0036-0039, 0067-0070, 0074-0084] teaches a hybrid system that has a computing unit and a noise amplification unit… standard transistors are used in the computing unit whereas transistors with near-zero V.sub.t are used in the noise amplification unit… noise generated by the amplifier circuit is used to generate a stream of random numbers)
Rad and Hekmatshoartabari are analogous art because they are from the same field of endeavor secure communications.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Rad and Hekmatshoartabari before him or her, to modify the method of Rad to include the noise generation of Hekmatshoartabari because it will allow for the noise to be used to generate truly random numbers (rather than pseudo-random numbers), usable for encryption.
The motivation for doing so would be [“high-speed low-power random number generation using physical devices are desirable because they are compatible with the semiconductor industry and can produce truly random numbers”] (Paragraph 0002-0005 by Hekmatshoartabari)].
Therefore, it would have been obvious to combine Rad and Hekmatshoartabari to obtain the invention as specified in the instant claim.
Claim 24 additionally discloses: A computer program product embodied in a non-transitory computer readable medium (Rad [0140] software or code can be embodied in any non-transitory computer-readable medium)
Claim 25 additionally discloses: A computer system for data manipulation comprising (Rad [0140] a processor in a computer system)
Regarding claim 3,
Rad in view of Hekmatshoartabari discloses: The method of claim 1 wherein keys used for the key-based shuffling and the key-based unshuffling comprise permutation patterns. (Rad [0006-0012, 0032, 0065-0067, 0073-0082, 0105-0107, 0118-0120] teaches the key based shuffling/unshuffling can use mathematical relationships/algorithms (permutation patterns) to perform the shuffling/unshuffling)
Regarding claim 4,
Rad in view of Hekmatshoartabari discloses: The method of claim 3 wherein the keys are selected for use by a random key index generator. (Rad [0006-0012, 0037-0051, Fig. 1-110] teaches storage and retrieval of randomly generated (pre-calculated, stored, and indexed) keys.
Regarding claim 6,
Rad in view of Hekmatshoartabari discloses: The method of claim 4 wherein the index selects a pre-calculated, stored key. (Rad [0006-0012, 0037-0051, Fig. 1-110] teaches storage and retrieval of randomly generated (pre-calculated, stored, and indexed) keys.
Regarding claim 8,
Rad in view of Hekmatshoartabari discloses: The method of claim 1 wherein a same key used for the key-based shuffling is used for the key-based unshuffling. (Rad [0006-0012, 0032, 0065-0068, 0073-0082, 0105-0107, 0118-0120] teaches the first encryption key is reused for subsequent images)
Regarding claim 9,
Rad in view of Hekmatshoartabari discloses: The method of claim 8 wherein the same key used for the key-based shuffling that is also used for the key-based unshuffling is applied to a block of data. (Rad [0006-0012, 0032, 0065-0068, 0073-0082, 0105-0107, 0118-0120] teaches retrieve of a file encrypting (shuffling) the file to generate an encrypted (shuffled) file and reversing the process using key-based techniques)
Regarding claim 12,
Rad in view of Hekmatshoartabari discloses: The method of claim 1 wherein the key-based shuffling is performed on a bit basis. (Rad [0006-0012, 0073-0082, 0092-0094] teaches bid-plane shuffling and unshuffling)
Regarding claim 13,
Rad in view of Hekmatshoartabari discloses: The method of claim 1 wherein the key-based unshuffling is performed on a bit basis. (Rad [0006-0012, 0073-0082, 0092-0094] teaches bit-plane shuffling and unshuffling)
Regarding claim 19,
Rad in view of Hekmatshoartabari discloses: The method of claim 1 further comprising
Rad does not explicitly teach: injecting noise among the low-reliability cells, based on the pre-characterized noise level.
However, in the same field of endeavor Hekmatshoartabari teaches: injecting noise among the low-reliability cells, based on the pre-characterized noise level. (Hekmatshoartabari [Fig. 18, 0006-0010, 0036-0039, 0067-0070, 0074-0084] teaches a hybrid system that has a computing unit and a noise amplification unit… standard transistors are used in the computing unit whereas transistors with near-zero V.sub.t are used in the noise amplification unit… noise generated by the amplifier circuit is used to generate a stream of random numbers)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify with Hekmatshoartabari for similar reasons as cited in claim 1.
Regarding claim 20,
Rad in view of Hekmatshoartabari discloses: The method of claim 19 wherein the
Rad does not explicitly teach: injecting noise is further controlled by a random noise generator.
However, in the same field of endeavor Hekmatshoartabari teaches: injecting noise is further controlled by a random noise generator. (Hekmatshoartabari [Fig. 18, 0006-0010, 0036-0039, 0067-0070, 0074-0084] teaches a hybrid system that has a computing unit and a noise amplification unit… standard transistors are used in the computing unit whereas transistors with near-zero V.sub.t are used in the noise amplification unit… noise generated by the amplifier circuit is used to generate a stream of random numbers)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify with Hekmatshoartabari for similar reasons as cited in claim 1.
Regarding claim 21,
Rad in view of Hekmatshoartabari discloses: The method of claim 20 wherein the
Rad does not explicitly teach: random noise generator is used to provide a random value for the low-reliability cells.
However, in the same field of endeavor Hekmatshoartabari teaches: random noise generator is used to provide a random value for the low-reliability cells. (Hekmatshoartabari [Fig. 18, 0006-0010, 0036-0039, 0067-0070, 0074-0084] teaches a hybrid system that has a computing unit and a noise amplification unit… standard transistors are used in the computing unit whereas transistors with near-zero V.sub.t are used in the noise amplification unit… noise generated by the amplifier circuit is used to generate a stream of random numbers)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify with Hekmatshoartabari for similar reasons as cited in claim 1.
Regarding claim 22,
Rad in view of Hekmatshoartabari discloses: The method of claim 1 wherein the key-based unshuffling is performed during operation of the SRAM. (Rad [0006-0012, 0032-0037, 0065-0068, 0073-0082, 0105-0107, 0118-0120] teaches decrypting (unshuffling) can be performed by a computing device; [0135] teaches that the computing device can comprise SRAM)
Regarding claim 23,
Rad in view of Hekmatshoartabari discloses: The method of claim 22 wherein the unshuffling occurs before presentation of the data to SRAM data terminals. (Rad [0006-0012, 0032-0037, 0065-0068, 0073-0082, 0105-0107, 0118-0120] teaches decrypting (unshuffling) can be performed by a computing device. The decrypted data bay then be subject to read/write requests (presented to data terminals); [0135] teaches that the computing device can comprise SRAM)
Claims 2, 10-11, 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Rad (U.S. 20180165466), in view of Hekmatshoartabari (U.S. 20200364032), in further view of Ueng (U.S. 9058880).
Regarding claim 2,
Rad in view of Hekmatshoartabari discloses: The method of claim 1 wherein… the low-reliability storage cells are used to inject random noise. (Hekmatshoartabari [Abstract] a noise amplification unit configured to generate an amplified noise signal, wherein the noise amplification unit includes noise amplification unit transistors having a threshold voltage (V.sub.t,amp) of about 0)
Rad in view of Hekmatshoartabari does not explicitly disclose: the high-reliability storage cells are used to store most-significant bits (MSB) and keys
However, in the same field of endeavor Ueng discloses: the high-reliability storage cells are used to store most-significant bits (MSB) (Ueng [Abstract, Col 2 line 4-60] the most significant information bits are stored in the first memory; and least significant information bits are stored in the second memory) and keys (Rad [0135, Fig. 1-154] Key Storage]
Rad in view of Hekmatshoartabari and Ueng are analogous art because they are from the same field of endeavor, SRAM’s.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Rad in view of Hekmatshoartabari and Ueng before him or her, to modify the method of Rad in view of Hekmatshoartabari to include storing keys, which can be rendered useless when even flight errors, in the high reliability storage cells of Ueng in order to save resourced when errors matter less and to prevent errors when errors matters more.
The motivation for doing so would be [“In such a decoder, if only few errors occur, particularly in the LSBs, the memory deployment has negligible impact on the decoding performance…. As shown, the butterfly curve 31 of the first memory indicates a larger noise margin, resulting in fewer errors during operation”] (Col 2 line 34-63] by Ueng) “unequal bit-reliability information storage method according to the invention, more memories with different reliabilities can be used based on the significance of each bit to reduce the storage area and power while maintaining the overall performance of the system” (Col 3 line 7-18)].
Therefore, it would have been obvious to combine Rad in view of Hekmatshoartabari and Ueng to obtain the invention as specified in the instant claim.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify with Hekmatshoartabari for similar reasons as cited in claim 1.
Regarding claim 10,
Rad in view of Hekmatshoartabari discloses: The method of claim 1 wherein keys used for the key-based shuffling and the key-based unshuffling are (Rad [Fig. 1-154, 0006-0012, 0065-0067, 0075-0080] teaches that the shuffling can be based on a key)
Rad in view of Hekmatshoartabari does not explicitly disclose: stored in high-reliability storage cells.
However, in the same field of endeavor Ueng discloses: stored in high-reliability storage cells. (Ueng [Abstract, Col 2 line 4-60] the most significant information bits are stored in the first memory; and least significant information bits are stored in the second memory)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify with Ueng for similar reasons as cited in claim 2.
Regarding claim 11,
Rad in view of Hekmatshoartabari and Ueng discloses: The method of claim 10 wherein the keys are generated outside of the SRAM. (Rad [0006-0012, 0032-0037, 0065-0068, 0073-0082, 0105-0107, 0118-0120] teaches that the client application can prompt the user for a key (generated key outside of the SRAM) or the client application can generate the key based on biometric information obtained from the user; [0135] teaches that the memory being used can be SRAM)
Regarding claim 14,
Rad in view of Hekmatshoartabari and Ueng discloses: The method of claim 1 wherein
Rad in view of Hekmatshoartabari does not explicitly disclose: the high-reliability storage cells are used to store most significant bits (MSBs).
However, in the same field of endeavor Ueng discloses: the high-reliability storage cells are used to store most significant bits (MSBs). (Ueng [Abstract, Col 2 line 4-60] the most significant information bits are stored in the first memory; and least significant information bits are stored in the second memory)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify with Ueng for similar reasons as cited in claim 2.
Regarding claim 15,
Rad in view of Hekmatshoartabari and Ueng discloses: The method of claim 14 wherein
Rad in view of Hekmatshoartabari does not explicitly disclose: the low-reliability storage cells are used to store least significant bits (LSBs).
However, in the same field of endeavor Ueng discloses: the low-reliability storage cells are used to store least significant bits (LSBs). (Ueng [Abstract, Col 2 line 4-60] the most significant information bits are stored in the first memory; and least significant information bits are stored in the second memory)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify with Ueng for similar reasons as cited in claim 2.
Regarding claim 16,
Rad in view of Hekmatshoartabari and Ueng discloses: The method of claim 15 wherein the data is processed on a byte basis. (Rad [0006-0012, 0073-0082, 0092-0094] teaches bit-plane shuffling and unshuffling including 8-bits)
Regarding claim 17,
Rad in view of Hekmatshoartabari and Ueng discloses: The method of claim 16 wherein
Rad in view of Hekmatshoartabari does not explicitly disclose: the high-reliability storage cells store the four MSBs of a byte.
However, in the same field of endeavor Ueng discloses: the high-reliability storage cells store the four MSBs of a byte. (Ueng [Abstract, Fig. 1-11, Col 2 line 4-28, Col 2 line 36-60] the most significant information bits are stored in the first memory; and least significant information bits are stored in the second memory)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify with Ueng for similar reasons as cited in claim 2.
Regarding claim 18,
Rad in view of Hekmatshoartabari and Ueng discloses: The method of claim 16 wherein
Rad in view of Hekmatshoartabari does not explicitly disclose: the low-reliability storage cells store the four LSBs of a byte.
However, in the same field of endeavor Ueng discloses: the low-reliability storage cells store the four LSBs of a byte. (Ueng [Abstract, Fig. 1-12, Col 2 line 4-28, Col 2 line 36-60] the most significant information bits are stored in the first memory; and least significant information bits are stored in the second memory)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify with Ueng for similar reasons as cited in claim 2.
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Rad (U.S. 20180165466), in view of Hekmatshoartabari (U.S. 20200364032), in further view of Alagappan (U.S. 20240110959)
Regarding claim 5,
Rad in view of Hekmatshoartabari discloses: The method of claim 4 wherein
While Rad in view of Hekmatshoartabari teaches hardware based random number generation, it does not explicitly teach using multiplexers and shift registers Rad in view of Hekmatshoartabari does not explicitly disclose: the random key index generator is based on one or more linear feedback shift registers.
However, in the same field of endeavor Alagappan discloses: the random key index generator is based on one or more linear feedback shift registers. (Alagappan [0046] As shown in FIG. 8, clock dithering circuitry 50 may include a chain of delay circuits 52 (e.g., buffers, inverter, or other delay components), a multiplexing circuit such as multiplexer 54 having inputs connected to different tap points along the delay chain and having a control input configured to receive signals from a linear feedback shift register (LFSR) 56. Linear feedback shift register 56 may have a clock input configured to receive input clock signal Clk_in and an output on which a pseudo random number sequence is generated. By feeding the pseudo random number sequence generated by the LSFR 56 to the control input of multiplexer 54, the delay of Clk_in can be shuffled each clock cycle. This effectively changes the period of control signal ϕa every clock cycle)
Rad in view of Hekmatshoartabari and Alagappan are analogous art because they are from the same field of endeavor random number generation.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Rad in view of Hekmatshoartabari and Alagappan before him or her, to modify the method of Rad in view of Hekmatshoartabari to include the generation of random numbers using hardware such as shift registers and multiplexers of Alagappan because it will for shuffling to be performed each clock cycle with accurate frequency measurements.
The motivation for doing so would be [“ the delay of Clk_in can be shuffled each clock cycle. This effectively changes the period of control signal ϕa every clock cycle. By changing the duration of the charging phase every clock cycle and passing the output of comparator through a digital majority voting circuit or through a digital averaging filter that can be included within digital output logic, the power supply rejection ratio of voltage based frequency monitoring circuit can be improved.”] (Paragraph 0028, 0046-0047, 0060 by Alagappan)].
Therefore, it would have been obvious to combine Rad in view of Hekmatshoartabari and Alagappan to obtain the invention as specified in the instant claim.
Regarding claim 7,
Rad in view of Hekmatshoartabari discloses: The method of claim 3 wherein
Rad in view of Hekmatshoartabari does not explicitly disclose: the permutation patterns are applied to data using a mux-based shuffler and/or unshuffler.
However, in the same field of endeavor Alagappan discloses: the permutation patterns are applied to data using a mux-based shuffler and/or unshuffler. (Alagappan [0046] As shown in FIG. 8, clock dithering circuitry 50 may include a chain of delay circuits 52 (e.g., buffers, inverter, or other delay components), a multiplexing circuit such as multiplexer 54 having inputs connected to different tap points along the delay chain and having a control input configured to receive signals from a linear feedback shift register (LFSR) 56. Linear feedback shift register 56 may have a clock input configured to receive input clock signal Clk_in and an output on which a pseudo random number sequence is generated. By feeding the pseudo random number sequence generated by the LSFR 56 to the control input of multiplexer 54, the delay of Clk_in can be shuffled each clock cycle. This effectively changes the period of control signal ϕa every clock cycle)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify with Alagappan for similar reasons as cited in claim 5.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's
disclosure.
Methods for noise margin analysis of conventional 6 T and 8 T SRAM cell (April 17, 2023) - Aastha Gupta, Ravi Sindal, Priyanka Sharma, Ashish Panchal, Vaibhav Neema – Teaches: the methods for calculating noise margin of conventional 6 transistor (6 T) and 8 transistor (8 T) SRAM cell. For calculation of noise margins in memory cell, this paper considered butterfly analysis and noise-curve methods. From the simulation results obtained from the above-mentioned method, the findings shows that 8 transistor SRAM cell provides higher read noise margin than 6 transistor SRAM cell. The aim of this paper is to verify and validate butterfly analysis and noise-curve methods for calculation of noise margins in memory cells.
TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs (November 20, 2022) – Ismail Emir Yuksel, Ataberk Olgun, Behzad Salami, Nisa Bostancı, Yahya Can Tugrul, A. Giray Yaglıkc, Nika Mansouri Ghiasi, Onur Mutlu, and Oguz Ergin – Teaches: a new technique to generate true random numbers in SRAM devices by underscaling the supply voltage of an SRAM device. Underscaling the supply voltage of the SRAM blocks below the manufacturer recommended margin and accessing the SRAM cells using the nominal latency violates the required access latency, and thus causes an access failure.
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THOMAS A. CARNES
Examiner
Art Unit 2436
/THOMAS A CARNES/ Examiner, Art Unit 2436 /SHEWAYE GELAGAY/Supervisory Patent Examiner, Art Unit 2436