Prosecution Insights
Last updated: October 01, 2026
Application No. 18/820,725

SEMICONDUCTOR MANUFACTURING APPARATUS AND CONTROL METHOD THEREOF

Non-Final OA §112
Filed
Aug 30, 2024
Priority
Feb 15, 2024 — JP 2024-021273
Examiner
PATEL, JIGNESHKUMAR C
Art Unit
Tech Center
Assignee
KIOXIA Corporation
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
372 granted / 469 resolved
+19.3% vs TC avg
Strong +21% interview lift
Without
With
+21.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
21 currently pending
Career history
485
Total Applications
across all art units

Statute-Specific Performance

§101
14.6%
-25.4% vs TC avg
§103
53.6%
+13.6% vs TC avg
§102
19.1%
-20.9% vs TC avg
§112
9.5%
-30.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 469 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Application 2. Claim 1-20 have been examined in this application. This communication is the first action on the merits. Drawings 3. The drawings filed on 8/30/24 are acceptable for examination proceedings. Claim Rejections - 35 USC § 112 4. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 5. Regarding claim 1, 9-10, 15-17, and 19, the phrase "boding target" renders the claim indefinite because it is unclear whether the limitation(s) following the phrase are part of the claimed invention. See MPEP § 2173.05(d). The meaning of the claim limitation that include the phrase “bonding target” is unknown because after interpreting the claim in view of specification one of ordinary skill in the art would not understand the boundaries of the invention with reasonable certainty. 6. Claim 2-14 and 16-20 are also rejected under 112(b) due to their direct/indirect dependency over the claim 1, and 15 respectively. 7. Claim 2-14 recites the limitation "The apparatus" in line. 1. There is insufficient antecedent basis for this limitation in the claim. Note: Examiner suggests to correct it to “The semiconductor manufacturing apparatus” in order to overcome the rejection 8. Claim 16-20 recites the limitation "The method" in line. 1. There is insufficient antecedent basis for this limitation in the claim. Note: Examiner suggests to correct it to “The control method” in order to overcome the rejection. Allowable Subject Matter Claim 1-20 are rejected under 35 U.S.C 112(b) rejection as discussed above and would be allowable over the prior art once overcome the rejection. There is no prior art rejection provided for claim 1-20. The closest prior art Yoon (Pub: 2009/0020229) disclose a semiconductor chip bonding apparatus, and more particularly, to an apparatus to bond a semiconductor chip on a lead frame or a substrate such as a PCB (Para. [0003]). Onituka (Pub: 2006/0243391) disclose a pressure bonding machine which can perform a pressure bonding operation upon a plurality of substrates at a low cost and efficiently (Para. [0006]-[0007]). Yamasaki (Pat: 12217963) disclose A bonding apparatus configured to bond a first substrate and a second substrate includes: a first holder configured to hold the first substrate; a second holder disposed to face the first holder in a vertical direction, and configured to hold the second substrate; a processing vessel accommodating the first holder and the second holder therein; and a horizontal position adjuster provided outside the processing vessel and connected to the first holder via a support supporting the first holder, the horizontal position adjuster being configured to adjust a horizontal position of the first holder (Abstract). Sato (Pat: 5985064) disclose a chip compression-bonding apparatus and a chip compression-bonding method in which a compression-bonding force can be accurately controlled (Col 1, Ln. 43-46). Hoshi (Pat: 5273553) disclose a method for bonding at least two semiconductor wafers to each other which comprises the steps of warping one of the semiconductor wafers, bringing the warped semiconductor wafer into contact with the other semiconductor wafer at one contact point, and reducing pressure in an atmosphere surrounding the semiconductor wafers to flatten the warped semiconductor wafer. An apparatus for bonding wafers using the above bonding method comprises a first wafer holder for warping and holding one of two wafers and a second wafer holder for holding the other wafer. First and second covers are attached so as to surround the first and second wafer holders. The apparatus further comprises a shaft for rotating the first and second wafer holders so that one of the wafers contact the other wafer at one contact point and the first and second covers are connected to each other to form a chamber. A vacuum pump for reducing pressure in the chamber is connected to the chamber through an exhaust hole provided at one of the first and second covers (Abstract). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIGNESHKUMAR C PATEL whose telephone number is (571)270-0698. The examiner can normally be reached Monday - Friday, 7:00 AM - 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth M. Lo can be reached at (571)272-9774. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JIGNESHKUMAR C PATEL/Primary Examiner, Art Unit 2116
Read full office action

Prosecution Timeline

Aug 30, 2024
Application Filed
Sep 15, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+21.2%)
2y 9m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 469 resolved cases by this examiner. Grant probability derived from career allowance rate.

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