Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 8, 10-12, & 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2022/0189902) [Hereinafter Lee].
Regarding claim 1, Lee teaches A semiconductor package comprising:
a first substrate [fig. 2, substrate 400, para 51];
a second substrate [fig. 2, substrate 300, para 51] on the first substrate (fig. 2, 400) and electrically connected to the first substrate (fig. 2, 400);
a first semiconductor chip [fig. 2, chip 110, para 54; left-most chip], on the second substrate (fig. 2, 300);
a first underfill material layer [fig. 2, underfill layer 382, para 87] between the first semiconductor chip (fig. 2, 110) and the second substrate (fig. 2, 300);
a second semiconductor chip [fig. 2, chip 110, para 54; right most chip] on the second substrate (fig. 2, 300) and spaced apart from the first semiconductor chip (fig. 2, 110; left-most chip) in a horizontal direction [fig. 2];
a second underfill material layer (fig. 2, 382) between the second semiconductor chip (fig. 2, 110; right-most chip) and the second substrate (fig. 2, 300); and
an outermost layer [fig. 2, molding layer 800, para 97] conformally extending on and at least partially covering the first underfill material layer (fig. 2, 382) and the second underfill material layer (fig. 2, 382),
wherein the outermost layer [fig. 2, molding layer 800, para 97] at least partially covers a surface of the first underfill material layer (fig. 2, 382; left-most chip) at least partially exposed between the second substrate (fig. 2, 300) and the first semiconductor chip (fig. 2, 110; left-most chip) and at least partially covers a surface of the second underfill material layer (fig. 2, 382; right-most chip) at least partially exposed between the second substrate (fig. 2, 300) and the second semiconductor chip (fig. 2, 110; right-most chip).
Regarding claim 8, Lee teaches The semiconductor package of claim 1,
wherein the second substrate comprises an interposer substrate (fig. 2, 300, para 86],
an interconnection layer [fig. 2, redistribution structure 357, para 51] on an upper surface of the interposer substrate (fig. 2, 300), and
a through-electrode [fig. 2, through electrodes 330, para 81] extending through the interposer substrate (fig. 2, 300) in a vertical direction in which the second substrate (fig. 2, 300) is stacked on the first substrate (fig. 2, 400).
Regarding claim 10, Lee teaches The semiconductor package of claim 1,
wherein the second substrate (fig. 2, 300) comprises
a redistribution insulating layer [fig. 2, redistribution insulating layer 357_6, para 80] and a redistribution pattern [fig. 2, redistribution pads 357_2, para 80] within the redistribution insulating layer (fig. 2, 357_6).
Regarding claim 11, Lee teaches A semiconductor package comprising:
a first substrate [fig. 2, substrate 400, para 89];
a second substrate [fig. 2, substrate 300, para 51] on the first substrate (fig. 2, 400) and electrically connected to the first substrate (fig. 2, 400);
a first semiconductor chip [fig. 2, semiconductor chip 110, para 54; left-most chip] on the second substrate (fig. 2, 300);
a first underfill material layer [fig. 2, underfill layer 382, para 87] between the first semiconductor chip (fig. 2, 110; left-most chip) and the second substrate (fig. 2, 300); a
second semiconductor chip (fig. 2, 110; right-most chip) on the second substrate (fig. 2, 300) and apart from the first semiconductor chip in a horizontal direction (fig. 2);
a second underfill material layer (fig. 2, 382) between the second semiconductor chip (fig. 2, 110; right-most chip) and the second substrate (fig. 2, 300);
a molding member [fig. 2, molding layer 800, para 97] at least partially surrounding the first semiconductor chip (fig. 2, 110; left-most chip) and the second semiconductor chip (fig. 2, 110; right-most chip) on an upper surface of the second substrate (fig. 2, 300) that is opposite the first substrate (fig. 2, 400); and
an outermost layer [fig. 2, heat dissipating member 950/900, para 98/100] distinct from the molding member (fig. 2, 800) and at least partially covering the molding member (fig. 2, 800) and the second substrate (fig. 2, 300),
wherein the outermost layer (fig. 2, 950/900) at least partially covers side and upper surfaces of the molding member (fig. 2, 800) and
a side surface of the second substrate (fig. 2, 300) relative to the upper surface of the second substrate (fig. 2, 300).
Regarding claim 12, Lee teaches The semiconductor package of claim 11,
wherein the outermost layer (fig. 2, 950/900) covers an entire surface exposed vertically upward from the upper surface of the second substrate (fig. 2, 300).
Regarding claim 17, Lee teaches The semiconductor package of claim 11,
wherein the second substrate (fig. 2, 300) comprises an interposer substrate [para 86],
an interconnection layer [fig. 2, redistribution structure 357, para 80] on an upper surface of the interposer substrate (fig. 2, 300), and
a through-electrode [fig. 2, through electrode 330, para 81] extending through the interposer substrate (fig. 2, 300) in a vertical direction in which the second substrate (fig. 2, 300) is stacked on the first substrate (fig. 2, 400).
Regarding claim 18, Lee teaches A semiconductor package comprising:
a first substrate [fig. 2, substrate 400, para 89];
a second substrate [fig. 2, substrate 300, para 51] on the first substrate (fig. 2, 400) and electrically connected to the first substrate (fig. 2, 400);
a stiffener [fig. 2, heat dissipating member 950, para 98] on the first substrate (fig. 2, 400) and spaced apart from the second substrate (fig. 2, 300) in a horizontal direction;
a first semiconductor chip [fig. 2, semiconductor chip 110, para 54; left-most chip] on the second substrate (fig. 2, 300);
a first underfill material layer [fig. 2, underfill layer 382, para 87] between the first semiconductor chip (fig. 2, 110; left-most chip) and the second substrate (fig. 2, 300);
a second semiconductor chip (fig. 2, 110; right-most chip) on the second substrate (fig. 2, 300) and spaced apart from the first semiconductor chip (fig. 2, 110; left-most chip) in the horizontal direction;
a second underfill material layer (fig. 2, 382) between the second semiconductor chip (fig. 2, 110; right-most chip) and the second substrate (fig. 2, 300);
a molding member [fig. 2, molding layer 800, para 97] at least partially surrounding the first semiconductor chip (fig. 2, 110; left-most chip) and the second semiconductor chip (fig. 2, 110; right-most chip) on an upper surface of the second substrate (fig. 2, 300); and
an outermost layer [fig. 2, TIM 900, para 100] distinct from the molding member (fig. 2, 800) and at least partially covering the molding member (fig. 2, 800), the first substrate (fig. 2, 400), and the second substrate (fig. 2, 300),
wherein the outermost layer (fig. 2, 900) at least partially covers side and upper surfaces of the molding member (fig. 2, 800), at least partially covers a side surface of the second substrate (fig. 2, 300), and at least partially covers at least a portion of an upper surface of the first substrate (fig. 2, 400),
wherein the side surface of the molding member (fig. 2, 800) is substantially coplanar with the side surface of the second substrate (fig. 2, 300), and
wherein the upper surface of the molding member (fig. 2, 800) is substantially coplanar with the upper surface of the first semiconductor chip (fig. 2, 110; left-most chip) and the upper surface of the second semiconductor chip (fig. 2, 110; right-most chip).
Regarding claim 19, Lee teaches The semiconductor package of claim 18,
wherein the second substrate (fig. 2, 300) comprises a redistribution insulating layer [fig. 2, redistribution insulating layer 357_6, para 80] and
a redistribution pattern [fig. 2, redistribution pads 357_2, para 80] within the redistribution insulating layer (fig. 2, 357_6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2-3, 5, & 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claims 1, 8, 10-12, & 17-19 and further in view of Choi et al. (US 2014/0299980) [Hereinafter Choi].
Regarding claim 2, Lee teaches The semiconductor package of claim 1,
wherein the outermost layer (fig. 2, 800) at least partially covers an upper surface and a side surface of each of the first semiconductor chip (fig. 2, 110; left-most chip) and the second semiconductor chip (fig. 2, 110; right-most chip) relative to an upper surface of the first substrate (fig. 2, 400).
Lee fails to explicitly disclose wherein the outermost layer at least partially covers an upper surface of each of the first semiconductor chip and the second semiconductor chip relative to an upper surface of the first substrate.
However, Choi teaches wherein the outermost layer [fig. 17, TIM layer 92, para 44] at least partially covers an upper surface of each of the first semiconductor chip [fig. 17, semiconductor chips 31, para 83] and the second semiconductor chip [fig. 17, semiconductor chips 31, para 83] relative to an upper surface of the first substrate [fig. 17, carrier 6, para 86].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the outermost layer to cover an upper surface of the semiconductor chips.
Regarding claim 3, Lee/Choi teaches The semiconductor package of claim 2,
wherein the outermost layer (Choi, fig. 17, 92) covers an entire surface exposed upwardly in a vertical direction from the upper surface of the first substrate (Choi, fig. 17, 6).
Regarding claim 5, Lee teaches The semiconductor package of claim 1,
wherein the outermost layer comprises an oxidation prevention layer [fig. 2, molding layer 800, para 97; wherein molding layer comprises EMC which is an oxidation prevention layer].
at least partially covering the first underfill material layer (fig. 2, 382) and the second underfill material layer (fig. 2, 382).
While Lee notes a heat dissipating member (fig. 2, 950) covering the oxidation prevention layer (fig. 2, 800).
Lee fails to explicitly disclose an oxidation/moisture absorption prevention layer at least partially covering the oxidation prevention layer.
Choi teaches an oxidation/moisture absorption prevention layer [fig. 18, heat spreader 94, para 83, “The heat spreader 94 may include a material having good heat transmission characteristics or high mechanical strength, for example, Cu, Al, W, TiN, TaN, Ni, or a combination thereof.”; wherein Ni, TiN, and TaN are barrier materials that block oxidation and moisture] at least partially covering the oxidation prevention layer [fig. 18, TIM layer 92, para 83].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the outermost layer to comprise an oxidation prevention layer and an oxidation moisture absorption prevention layer covering the oxidation prevention layer to fully seal the device against water and ionization thereby enhancing the reliability of the device.
Regarding claim 7, Lee teaches The semiconductor package of claim 1,
wherein the outermost layer comprises an oxidation prevention layer [fig. 2, molding layer 800, para 97; wherein molding layer comprises EMC which is an oxidation prevention layer]. at least partially covering each of the first and second underfill material layers (fig. 2, 382).
Lee fails to explicitly disclose an electromagnetic interference (EMI) shielding layer at least partially covering the oxidation prevention layer, and
an oxidation/moisture absorption prevention layer at least partially covering the EMI shielding layer.
However Choi teaches an electromagnetic interference (EMI) shielding layer [fig. 26, heat spreader 94, para 83] at least partially covering the oxidation prevention layer [fig. 26, TIM layer 92, para 81; wherein curing resin prevents oxidation], and
an oxidation/moisture absorption prevention layer [fig. 26, encapsulant 96, para 92] at least partially covering the EMI shielding layer (fig. 26, 94).
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the device to comprise an EMI shielding layer and an oxidation/moisture prevention layer covering the EMI shield layer to provide crosstalk reduction while also increasing the temperature tolerance of the device due to the EMI shield comprising a metal plate.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claims 1, 8, 10-12, & 17-19 and further in view of Jung et al. (US 2017/0358716)
Regarding claim 4, Lee teaches The semiconductor package of claim 1,
wherein the outermost layer [fig. 2, molding layer 800, para 97] comprises an oxidation/moisture absorption prevention layer [fig. 2, molding layer 800, para 97; wherein molding layer comprises EMC which is an oxidation/moisture absorption prevent layer].
Lee fails to explicitly disclose the oxidation/moisture absorption prevention layer comprises a titanium dioxide.
Jung teaches the oxidation/moisture absorption prevention layer [fig. 1/2, white molding compound, para 43-44 comprises a titanium dioxide “Titanium dioxide (TiO2) . . . may be used as the white pigment.”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the EMC to comprise titanium dioxide as a white pigment to prevent discoloration during manufacturing as standard epoxy resins tend to turn yellow or brown under prolonged thermal or UV exposure.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee & Choi as applied to claims 2-3, 5, & 7 and further in view of Hwang et al. (US 2008/0315402).
Regarding claim 6, Lee/Choi teaches The semiconductor package of claim 5, further comprising
an adhesive layer between the oxidation prevention layer and the oxidation/moisture absorption prevention layer.
While Lee specifically notes a thermal interface material layer (fig. 2, 900, para 100; “The TIM 900 may include paste or a film.”) between the epoxy mold compound layer (fig. 2, 800) and the heat dissipating member (fig. 2, 950).
Lee is silent regarding whether the TIM material is adhesive.
However Hwang teaches a thermal interface adhesive layer [fig. 7, thermal interface adhesive 160, para 89] coated on a first surface “The thermal interface adhesive 160 may be coated on a first surface of the heat sink 113 to adhere the first semiconductor packages 131 . . .the thermal interface adhesive 160 also functions to transmit heat of the first semiconductor packages 131 . . .toward the heat sink 113.”
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the TIM layer of Lee to comprise adhesive material to adhere the semiconductor packages and oxidation prevention layer to the heat sink to transmit heat of the semiconductor chips toward the heat sink.
Claim(s) 9 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claims 1, 8, 10-12, & 17-19 and further in view of Choi et al. (US 2021/0249327)
Regarding claim 9, Lee teaches The semiconductor package of claim 1,
the second substrate (fig. 2, 300) comprises a redistribution insulating layer [fig. 2, redistribution insulating layer 357_6, para 80] and a redistribution pattern [fig. 2, redistribution pads 357_2, para 80] within the redistribution insulating layer (fig. 2, 357_6).
While Lee notes the first substrate (fig. 2, 400) may comprise a baseboard and include a printed circuit board.
Lee fails to explicitly disclose wherein the first substrate comprises a cavity therein,
the cavity is provided with a bridge chip.
Choi_2021 teaches wherein the first substrate [fig. 13, substrate 170, para 111-112] comprises a cavity therein,
the cavity is provided with a bridge chip [fig. 13, bridge 181, para 111].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the base substrate to comprise a bridge chip to enable high speed communication between multiple semiconductor dies while keeping manufacturing costs low.
Regarding claim 20, Lee teaches The semiconductor package of claim 18,
the second substrate (fig. 2, 300) comprises a redistribution insulating layer [fig. 2, redistribution insulating layer 357_6, para 80] and
a redistribution pattern [fig. 2, redistribution pads 357_2, para 80] within the redistribution insulating layer (fig. 2, 357_6).
Lee fails to explicitly disclose wherein the first substrate comprises a cavity therein,
the cavity is provided with a bridge chip.
Choi_2021 teaches wherein the first substrate [fig. 13, substrate 170, para 111-112] comprises a cavity therein,
the cavity is provided with a bridge chip [fig. 13, bridge 181, para 111].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the base substrate to comprise a bridge chip to enable high speed communication between multiple semiconductor dies while keeping manufacturing costs low.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claims 1, 8, 10-12, & 17-19 and further in view of Morimoto (JP2007115810A).
Regarding claim 13, Lee teaches The semiconductor package of claim 11, wherein the outermost layer comprises
an oxidation/moisture absorption prevention layer, and
the oxidation/moisture absorption prevention layer comprises a titanium dioxide.
While Lee notes the outermost layer (fig. 2, 950/900, para 98) comprises a heat sink.
Lee is silent whether the heat sink (fig. 2, 950) comprises an oxidation/moisture absorption prevention layer comprising titanium dioxide.
However, Morimoto teaches [para 8, “a heat sink having excellent heat dissipation can be obtained as a result of coating a heat sink with a titanium dioxide aqueous solution and causing fine particles of titanium dioxide to be present on the surface of the heat sink.”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the outermost layer (heat sink) to comprise an oxidation/moisture absorption prevention layer comprising titanium dioxide for excellent heat dissipation and fully sealing the device thereby enhancing reliability of the device.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claims 1, 8, 10-12, & 17-19 and further in view of Fan et al. (CN 1912046A) & Morimoto (JP2007115810A)
Regarding claim 14, Lee teaches The semiconductor package of claim 11.
While Lee notes the outermost layer (fig. 2, 950/900) to comprise a thermal interface layer (fig. 2, 900, para 100) at least partially covering the molding member (fig. 2, 800).
Lee is silent regarding the material of the thermal interface material (TIM) layer.
Therefore, Lee fails to explicitly disclose wherein the outermost layer comprises an oxidation prevention layer at least partially covering the molding member.
However, Fan teaches a thermal interface material which comprises “ . . . silicone, silicone oil, mineral oil, epoxy resin, sodium silicate or polyester.” ; wherein all listed materials prevent oxidation to varying degrees].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the thermal interface material layer of Lee (fig. 2, 900) to comprise a material that prevents oxidation to protect metal interconnects from reacting with oxygen and moisture thereby ensuring reliability of the device.
Furthermore, while Lee notes the outermost layer (fig. 2, 950/900, para 98) comprises a heat sink.
Lee is silent whether the heat sink (fig. 2, 950) comprises an oxidation/moisture absorption prevention layer.
Therefore Lee/Fan fails to explicitly disclose an oxidation/moisture absorption prevention layer at least partially covering the oxidation prevention layer.
However, Morimoto teaches [para 8, “a heat sink having excellent heat dissipation can be obtained as a result of coating a heat sink with a titanium dioxide aqueous solution and causing fine particles of titanium dioxide to be present on the surface of the heat sink.”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the outermost layer (heat sink) to comprise an oxidation/moisture absorption prevention layer for excellent heat dissipation and fully sealing the device thereby enhancing reliability of the device.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claims 1, 8, 10-12, & 17-19 and further in view of Fan & Choi.
Regarding claim 15, Lee teaches The semiconductor package of claim 11,
While Lee notes the outermost layer (fig. 2, 950/900) to comprise a thermal interface layer (fig. 2, 900, para 100) at least partially covering the molding member (fig. 2, 800).
Lee is silent regarding the material of the thermal interface material (TIM) layer.
Therefore, Lee fails to explicitly disclose wherein the outermost layer comprises an oxidation prevention layer at least partially covering the molding member.
However, Fan teaches a thermal interface material which comprises “ . . . silicone, silicone oil, mineral oil, epoxy resin, sodium silicate or polyester.” ; wherein all listed materials prevent oxidation to varying degrees].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the thermal interface material layer of Lee (fig. 2, 900) to comprise a material that prevents oxidation to protect metal interconnects from reacting with oxygen and moisture thereby ensuring reliability of the device.
Lee/Fan fails to explicitly disclose an electromagnetic interference (EMI) shielding layer at least partially covering the oxidation prevention layer, and
an oxidation/moisture absorption prevention layer at least partially covering the EMI shielding layer.
However Choi teaches an electromagnetic interference (EMI) shielding layer [fig. 26, heat spreader 94, para 83] at least partially covering the oxidation prevention layer [fig. 26, TIM layer 92, para 81; wherein curing resin prevents oxidation], and
an oxidation/moisture absorption prevention layer [fig. 26, encapsulant 96, para 92] at least partially covering the EMI shielding layer (fig. 26, 94).
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the device to comprise an EMI shielding layer and an oxidation/moisture prevention layer covering the EMI shield layer to provide crosstalk reduction while also increasing the temperature tolerance of the device due to the EMI shield comprising a metal plate.
Allowable Subject Matter
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 16 Lee/Fan/Choi teaches the semiconductor package of claim 15,
wherein a first adhesive layer is between the oxidation prevention layer and the EMI shielding layer.
The prior art of record fails to explicitly disclose a second adhesive layer is between the EMI shielding layer and the oxidation/moisture absorption prevention layer.
Thereby claim 16 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/FELIX B ANDREWS/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
