CTNF 18/820,907 CTNF 83016 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statements (IDS) submitted on December 5, 2024, April 25, 2025, October 20, 2025, and February 4, 2026 were filed after the filing date of the application on August 30, 2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Drawings 06-37 AIA The drawings were received on August 30, 2024 . These drawings are accepted . Claim Objections 07-29-01 AIA Claim s 2, 5, 13, and 18 are objected to because of the following informalities: Claim 2 recites, “The accelerator device of claim 1, the second base chiplet comprising an interface to a second logic chiplet…” but should recite, “The accelerator device of claim 1, wherein the second base chiplet comprising an interface to a second logic chiplet.” Claim 5 recites, “The accelerator device of claim 4, the second logic chiplet including a plurality of processor cores and a third interconnect structure to couple the second logic chiplet to the second interconnect fabric…” but should recite, “The accelerator device of claim 4, wherein the second logic chiplet including a plurality of processor cores and a third interconnect structure to couple the second logic chiplet to the second interconnect fabric.” Claim 13 recites, “The method of claim 12, the second logic chiplet comprising a plurality of processor cores to execute instructions…” but should recite, “The method of claim 12, wherein the second logic chiplet comprising a plurality of processor cores to execute instructions.” Claim 18 recites, “The graphics processing system of claim 16, the second logic chiplet including a plurality of processor cores…” but should recite, “The graphics processing system of claim 16, wherein the second logic chiplet including a plurality of processor cores.” Appropriate correction is required. Double Patenting 08-33 AIA The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-36 AIA Claim s 1, 5, 6, 11, 13, and 14 are rejected on the ground of non-statutory double patenting as being unpatentable over claim s 1 and 17 of U.S. Patent No. 12,112,398 in view of Carlson et al. (US 9,886,275). Please see the tables below . Present Application #18/820,907 1 5 6 11 13 14 U.S. Patent #12,112,398 1 1 1 17 17 17 Present Application #18/820,907 Claim 1 U.S. Patent #12,112,398 Claim 1 An accelerator device comprising: An apparatus comprising: a package assembly including: a first base chiplet comprising: a first base chiplet comprising: a first interconnect fabric; and a first interconnect fabric, and a first plurality of level 3 (L3) cache banks coupled to or integrated with the first interconnect fabric; a first plurality of cache banks coupled to or integrated with the first interconnect fabric; a first logic chiplet stacked on the first base chiplet, the first logic chiplet comprising: a first logic chiplet stacked on the first base chiplet, the first logic chiplet comprising: a cluster of compute units for parallel execution of compute shader instructions or graphics shader instructions; and a cluster of compute units to perform parallel execution of compute shader instructions or graphics shader instructions; a first interconnect structure coupling the cluster of compute units to the first interconnect fabric; and a first interconnect structure to couple the cluster of compute units to the first interconnect fabric; a second base chiplet coupled to the first base chiplet by a second interconnect structure, a second base chiplet comprising: the second base chiplet comprising: a second interconnect fabric; and a second interconnect fabric, and a second plurality of L3 cache banks coupled to or integrated with the second interconnect fabric, a second plurality of cache banks coupled to or integrated with the second interconnect fabric; a second logic chiplet stacked on the second base chiplet, the second logic chiplet comprising: a plurality of application processor cores to execute instructions; and a third interconnect structure to couple the second logic chiplet to the second interconnect fabric, wherein the first logic chiplet is manufactured using a different process technology than that used to manufacture the first base chiplet and the second base chiplet. wherein the first logic chiplet is manufactured using a different process technology than that used to manufacture the first and second base chiplets. Claim 1 of the present application differs from claim 1 of the patent application in that claim 1 of the present application is broader in scope than claim 1 of the patent application, thus encompasses that of the patent application. Additionally, claim 1 of the present application recites its first base chiplet and second base chiplet to each comprise “a plurality of L3 cache banks” where claim 1 of the patent application recites its first base chiplet and second base chiplet to each comprise “a plurality of cache banks.” It is well known in the art that cache memory may comprise different levels of storage, e.g. L1, L2, and L3 caches (and optionally an L4 cache), with L1 cache as the lowest capacity but fastest, typically used as a dedicated storage, and L3 as the highest capacity but slowest, typically used for sharing storage. L3 cache are also well known for improving GPU utilization frame consistency, and workload efficiency, thus enhancing the performance of the system. For explicit teaching, Carlson et al. disclose a plurality of multi-core ICs, where a chip may comprise a plurality of L3 cache banks ( column 9, lines 20-21 ), where each multi-core IC may have identical layouts ( column 7, lines 65 thru column 8, lines 3 ), thus considered each multi-core IC may comprise the same components, e.g. a plurality of L3 cache banks. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the patent application’s plurality of cache banks as L3 cache banks to improve system performance as described above. Present Application #18/820,907 Claim 5 U.S. Patent #12,112,398 Claim 1 The accelerator device of claim 4, An apparatus comprising… …a second logic chiplet stacked on the second base chiplet, the second logic chiplet including a plurality of processor cores and the second logic chiplet comprising: a plurality of application processor cores to execute instructions; and a third interconnect structure to couple the second logic chiplet to the second interconnect fabric. a third interconnect structure to couple the second logic chiplet to the second interconnect fabric… Present Application #18/820,907 Claim 6 U.S. Patent #12,112,398 Claim 1 The accelerator device of claim 5, wherein An apparatus comprising… the plurality of processor cores includes a plurality of application processor cores to execute general-purpose instructions. …the second logic chiplet comprising: a plurality of application processor cores to execute instructions… Present Application #18/820,907 Claim 11 U.S. Patent #12,112,398 Claim 17 A method of assembling an accelerator device including a plurality of chiplets, the method comprising: A method of assembling an apparatus including a plurality of chiplets, the method comprising: assembling a package assembly including a first base chiplet comprising a first interconnect fabric and a first plurality of level 3 (L3) cache banks coupled to or integrated with the first interconnect fabric; assembling a package assembly including a first base chiplet comprising a first interconnect fabric and a first plurality of cache banks coupled to or integrated with the first interconnect fabric; stacking a first logic chiplet on the first base chiplet, the first logic chiplet comprising a cluster of compute units to perform parallel execution of compute shader instructions or graphics shader instructions; stacking a first logic chiplet on the first base chiplet, the first logic chiplet comprising a cluster of compute units to perform parallel execution of compute shader instructions or graphics shader instructions; coupling the cluster of compute units to the first interconnect fabric via a first interconnect structure; and coupling the cluster of compute units to the first interconnect fabric via a first interconnect structure; coupling the first base chiplet to a second base chiplet by a second interconnect structure, the second base chiplet comprising a second interconnect fabric and a second plurality of L3 cache banks coupled to or integrated with the second interconnect fabric, coupling the first base chiplet to a second base chiplet by a second interconnect structure, the second base chiplet comprising a second interconnect fabric and a second plurality of cache banks coupled to or integrated with the second interconnect fabric; stacking a second logic chiplet on the second base chiplet, the second logic chiplet comprising a plurality of application processor cores to execute instructions; and coupling the second logic chiplet to the second interconnect fabric via a third interconnect structure, wherein the first logic chiplet is manufactured using a different process technology than that used to manufacture the first base chiplet and the second base chiplet. wherein the first logic chiplet is manufactured using a different process technology than that used to manufacture the first base chiplet and the second base chiplet. Claim 11 of the present application differs from claim 17 of the patent application in that claim 11 of the present application is broader in scope than claim 17 of the patent application, thus encompasses that of the patent application. Additionally, claim 11 of the present application recites its first base chiplet and second base chiplet to each comprise “a plurality of L3 cache banks” where claim 17 of the patent application recites its first base chiplet and second base chiplet to each comprise “a plurality of cache banks.” It is well known in the art that cache memory may comprise different levels of storage, e.g. L1, L2, and L3 caches (and optionally an L4 cache), with L1 cache as the lowest capacity but fastest, typically used as a dedicated storage, and L3 as the highest capacity but slowest, typically used for sharing storage. L3 cache are also well known for improving GPU utilization frame consistency, and workload efficiency, thus enhancing the performance of the system. For explicit teaching, Carlson et al. disclose a plurality of multi-core ICs, where a chip may comprise a plurality of L3 cache banks ( column 9, lines 20-21 ), where each multi-core IC may have identical layouts ( column 7, lines 65 thru column 8, lines 3 ), thus considered each multi-core IC may comprise the same components, e.g. a plurality of L3 cache banks. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the patent application’s plurality of cache banks as L3 cache banks to improve system performance as described above. Present Application #18/820,907 Claim 13 U.S. Patent #12,112,398 Claim 17 The method of claim 12, A method of assembling an apparatus including a plurality of chiplets, the method comprising… the second logic chiplet comprising a plurality of processor cores to execute instructions. …the second logic chiplet comprising a plurality of application processor cores to execute instructions… Present Application #18/820,907 Claim 14 U.S. Patent #12,112,398 Claim 17 The method of claim 13, wherein A method of assembling an apparatus including a plurality of chiplets, the method comprising… the plurality of processor cores includes a plurality of application processor cores to execute general-purpose instructions. …the second logic chiplet comprising a plurality of application processor cores to execute instructions… Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 16-20 are allowed. Claims 1, 5, 6, 11, 13, and 14 would be allowable if the Double Patenting rejection may be overcome. Claims 2-4, 7-10, 12, and 15 are objected to as being dependent upon a rejected base claim, but would overcome the Double Patenting rejection if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03 AIA The following is an examiner’s statement of reasons for allowance: The present invention relates to a system and method of packaging, e.g. stacking, multiple heterogeneous chiplets. Prior art includes: Carlson et al. (US 9,886,275) disclose an accelerator device comprising: a first base chiplet comprising: a first interconnect fabric ( column 6, lines 13-17 notes inter-level connections between cores to cache directly connecting individual cores to cache, e.g. a mesh network ); and a first plurality of level 3 (L3) cache banks coupled to or integrated with the first interconnect fabric ( column 6, lines 13-17, where column 9, lines 20-21 notes a chip may comprise a mesh network and banks of L3 cache ); a first logic chiplet stacked on the first base chiplet, the first logic chiplet comprising: a cluster of compute units for parallel execution of compute shader instructions or graphics shader instructions ( column 9, lines 20-21 notes chip may comprise processors, where column 3, lines 60 thru column 4, lines 17 notes tiles may include processors which may further include functional units, e.g. arithmetic logic units (ALUs) for performing operations in parallel, and column 6, lines 10-61 notes processors may be multi-core processors ); and a first interconnect structure coupling the cluster of compute units to the first interconnect fabric ( column 3, lines 60-63 notes tiles includes sets of incoming wires 104A and outgoing wires 104B that form data paths 104 for communicating with neighboring tiles, and column 7, lines 15-32 further notes cores in the multi-core IC communicate with each other via a network of interconnect structures with nodes regularly distributed in close proximity to the core ); and a second base chiplet comprising; a second interconnect fabric; and a second plurality of L3 cache banks coupled to or integrated with the second interconnect fabric ( e.g. column 7, lines 65 thru column 8, lines 3 notes multi-core ICs share an identical layout, thus may be considered to have the same components, e.g. “interconnect fabric” and “plurality of L3 cache banks” noted for the first chiplet above ), wherein the first logic chiplet is manufactured using a different process technology than that used to manufacture the first base chiplet and the second base chiplet ( column 8, lines 46 thru column 9, lines 18 notes alternative where multi-core ICs may have different layouts ); Tripathi et al. (US 2014/0071140)(cited in the Information Disclosure Statement filed February 4, 2026) discloses “an accelerator device ( Figure 2 ) comprising: a first base chiplet comprising: a first interconnect fabric ( e.g. fabric 230 ), and a first plurality of level 3 (L3) cache banks coupled to or integrated with the first interconnect fabric ( e.g. memory interface 210 including cache 214 coupled to fabric 230 ); a first logic chiplet stacked on the first base chiplet, the first logic chiplet comprising: a cluster of compute units for parallel execution of compute shader instructions or graphics shader instructions ( e.g. one or more of video graphics controller 240, display controller 262, and/or media controller 266 ); a first interconnect structure coupling the cluster of compute units to the first interconnect fabric ( e.g. “interconnect structure” illustrated with double-headed arrows coupling each to fabric 230 ); a second base chiplet ( e.g. considered IC with processors 250, cache 252, and bus interface unit 254 ) comprising: a second interconnect fabric ( e.g. bus interface unit 254 ), and a second plurality of L3 cache banks coupled to or integrated with the second interconnect fabric ( e.g. cache 252 coupled to bus interface unit 254 ), wherein the first logic chiplet is manufactured using a different process technology than that used to manufacture the first and second base chiplets ; Rusu (US 2016/0092396) disclose a system and method of stacking a plurality of cores utilizing a uncore die and a core die; and DELACRUZ et al. (US 2018/0102251) (cited in the Information Disclosure Statement filed April 25, 2025) disclose a system and method of connecting a plurality of chiplets of different types. Although the prior art noted above discloses certain features of the claimed invention as outlined above, but fails to teach or suggest, singly or combined, the limitations of independent claims 1, 11, and 16 as recited as a whole (with portions of limitations not explicitly taught emphasized in italics above) . Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACINTA M CRAWFORD whose telephone number is (571)270-1539. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACINTA M CRAWFORD/Primary Examiner, Art Unit 2617 Application/Control Number: 18/820,907 Page 2 Art Unit: 2617 Application/Control Number: 18/820,907 Page 3 Art Unit: 2617 Application/Control Number: 18/820,907 Page 4 Art Unit: 2617 Application/Control Number: 18/820,907 Page 5 Art Unit: 2617 Application/Control Number: 18/820,907 Page 6 Art Unit: 2617 Application/Control Number: 18/820,907 Page 7 Art Unit: 2617 Application/Control Number: 18/820,907 Page 8 Art Unit: 2617 Application/Control Number: 18/820,907 Page 9 Art Unit: 2617 Application/Control Number: 18/820,907 Page 10 Art Unit: 2617 Application/Control Number: 18/820,907 Page 11 Art Unit: 2617 Application/Control Number: 18/820,907 Page 13 Art Unit: 2617 Application/Control Number: 18/820,907 Page 14 Art Unit: 2617 Application/Control Number: 18/820,907 Page 15 Art Unit: 2617
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