DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For Claim 20 (penultimate line), the electronics design under test appears to have antecedent basis in the preceding line.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 11-12, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sommers (US 2022/0116303).
For Claims 1, 11, and 20, Sommers teaches a method for data center switching fabric path emulation in an electronics design automation (EDA) environment, a system for data center switching fabric path emulation in an electronics design automation (EDA) environment, the system comprising: at least one processor and a memory (see paragraphs 31-32), and a non-transitory computer readable medium having stored thereon executable instructions (see paragraphs 31-32); the method comprising:
generating emulated data center traffic (see paragraphs 4, 24, 39);
at a path emulation element, modifying the emulated data center traffic to emulate passing of the emulated data center traffic through a data center switching fabric (see paragraphs 24, 55, 60);
outputting, by the path emulation element, the modified emulated data center traffic to an EDA emulator emulating an electronics design under test (see paragraphs 6-7, 48, 91); and
receiving and storing a response of electronics design under test to the modified emulated data center traffic (see paragraph 48).
For Claims 2 and 12, Sommers teaches the method wherein generating emulated data center traffic includes generating emulated traffic of a data center processing an artificial intelligence/machine learning (AI/ML) workload (see paragraphs 24, 39, 57).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3, 10, 13, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sommers (US 2022/0116303) as applied to claims 1 and 11 above, and further in view of Zhang et al. (US 2015/0172185).
For Claims 3 and 13, Sommers as applied above is not explicit as to, but Zhang teaches the method modifying the emulated data center traffic includes adding, to the emulated data center traffic, a packet timing parameter that controls a time at which a transactor of the EDA emulator provides an emulated data packet to the electronics design under test (see paragraph 12).
Thus it would have been obvious to one of ordinary skill in the art at the time the application was filed to manage timing as in Zhang when implementing the testing as in Sommers. The motivation would be to test how timing affects the system.
For Claims 10 and 19, Sommers as applied above is not explicit as to, but Zhang teaches the method wherein the path emulation element is implemented as a component of a transactor of the EDA emulator (see paragraph 12).
Thus it would have been obvious to one of ordinary skill in the art at the time the application was filed to configure the system as in Zhang when implementing the testing as in Sommers. One of ordinary skill would have been able to do so with the reasonably predictable result of managing input and output in a known manner.
Claim(s) 4, 9, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sommers (US 2022/0116303) as applied to claims 1 and 11 above, and further in view of Avci et al. (US 2016/0057061).
For Claims 4 and 14, Sommers as applied above is not explicit as to, but Avci teaches the method wherein the path emulation element is implemented as an inline device between a test traffic generator that generates the emulated data center traffic and the EDA emulator (see abstract, paragraphs 6-7, 44, Figure 4).
Thus it would have been obvious to one of ordinary skill in the art at the time the application was filed to implementing the path emulation as in Avci when configuring the system of Sommers. One of ordinary skill would have been able to do so with the reasonably predictable result of managing the path emulation in a known manner.
For Claim 9, Sommers as applied above is not explicit as to, but Avci teaches the method wherein the path emulation element is integrated within a test traffic generator that generates the emulated data center traffic (see abstract, paragraph 44, Figure 4).
Thus it would have been obvious to one of ordinary skill in the art at the time the application was filed to implementing the path emulation as in Avci when configuring the system of Sommers. One of ordinary skill would have been able to do so with the reasonably predictable result of managing the path emulation in a known manner.
Claim(s) 5-6 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sommers (US 2022/0116303) and Avci et al. (US 2016/0057061) as applied to claims 1, 4, 11, and 14 above, and further in view of Cillis et al. (US 2015/0234725).
For Claims 5 and 15, the references as applied above are not explicit as to, but Cillis teaches the method wherein the path emulation element is connected between virtual interfaces between the test traffic generator and the EDA emulator (see paragraphs 22-23, 37: virtual interfaces, emulation).
Thus it would have been obvious to one of ordinary skill in the art at the time the application was filed to configure path emulation as in Cillis when implementing the system of Sommers and Avci. One of ordinary skill in the art would have been able to do so with the reasonably predictable result of managing path emulation in a known manner.
For Claims 6 and 15, Sommers as applied above Is not explicit as to, but Avci further teaches the method wherein the path emulation element is implemented using a network device (netdev), an emulated switch, or a filter connected between the virtual interfaces (see abstract, paragraphs 6-7, 44).
Thus it would have been obvious to one of ordinary skill in the art at the time the application was filed implement the path as in Avci when implementing the system of Sommers. One of ordinary skill in the art would have been able to do so with the reasonably predictable result of managing path emulation in a known manner.
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sommers (US 2022/0116303) and Avci et al. (US 2016/0057061) as applied to claims 1, 4, 11, and 14 above, and further in view of Shevade et al. (US 2020/0244556).
For Claims 7 and 17, the references as applied above are not explicit as to, but Shevade teaches the method wherein the path emulation element is located in a tunnel between the test traffic generator and the EDA emulator (see paragraph 82, Figure 14).
Thus it would have been obvious to one of ordinary skill in the art at the time the application was filed to manage path emulation as in Shevade when implementing the system of Sommers and Avci. One of ordinary skill would have been able to do so with the reasonably predictable result of emulating a known type of path to test.
Claim(s) 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sommers (US 2022/0116303) and Avci et al. (US 2016/0057061) as applied to claims 1, 4, 11, and 14 above, and further in view of Zhang et al. (US 2015/0172185) and Sharma et al. (US 2013/0287033).
For Claims 8 and 18, the references as applied above are not explicit as to, but Zhang teaches the method wherein the path emulation element is configured to communicate emulator timing information from the EDA emulator to the test traffic generator (see paragraph 12).
Thus it would have been obvious to one of ordinary skill in the art at the time the application was filed to manage timing as in Zhang when implementing the testing as in Sommers. The motivation would be to dynamically test how timing affects the system.
The references as applied above are not explicit as to, but Sharma teaches the path emulation element is configured to propagate indications of backpressure (see paragraphs 27, 46).
Thus it would have been obvious to one of ordinary skill in the art at the time the application was filed to feedback backpressure indications as in Sharma when implementing the method of Sommers. The motivation would be to test how the system performs under varying loads.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Dhanapal et al. (US 2014/0026123) teaches a system for testing using packet timing events.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASSANDRA L DECKER whose telephone number is (571)270-3946. The examiner can normally be reached 7:30 am - 4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Faruk Hamza can be reached at 571-272-7969. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CASSANDRA L DECKER/Examiner, Art Unit 2466 6/9/2026
/FARUK HAMZA/Supervisory Patent Examiner, Art Unit 2466
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