Office Action Predictor
Last updated: April 16, 2026
Application No. 18/821,038

Gradually Reclaim Storage Space Occupied by a Proof of Space Plot in a Solid State Drive

Final Rejection §103§DP
Filed
Aug 30, 2024
Examiner
MACKALL, LARRY T
Art Unit
2139
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology, INC.
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
2y 7m
To Grant
94%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
661 granted / 779 resolved
+29.9% vs TC avg
Moderate +9% lift
Without
With
+8.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
31 currently pending
Career history
810
Total Applications
across all art units

Statute-Specific Performance

§101
7.0%
-33.0% vs TC avg
§103
50.2%
+10.2% vs TC avg
§102
24.8%
-15.2% vs TC avg
§112
7.6%
-32.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 779 resolved cases

Office Action

§103 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 of U.S. Patent No. 12,086,432 contains every element of claims 1-20 of the instant application and as such anticipates claims 1-20 of the instant application. Instant Application Claim U.S. Patent No. 12,086,432 Claim 1 10 2 10 3 18 4 10 5 10 6 11 7 12 8 14 9 13 10 1 11 1 12 9 13 1 14 1 15 2 16 3 17 4 18 5 19 19 20 20 “A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1, 2, 4, 10, 11, 13, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto (Pub. No. US 2017/0220292) in view of Cohen et al. (Pub. No. US 2021/0271667). Claim 1: Hashimoto discloses a device, comprising: an interface operable to communicate with a host system [fig. 2; par. 0028 – IFC 11. (“an interface controller (IFC) 11 configured to perform transmission and reception of signals to and from the host 3 via the interface 9, a RAM (Random Access Memory) 12 functioning as a semiconductor memory, a controller 10 configured to manage and control the flash memory 16, the RAM 12, and the IFC 11.”)]; a data storage medium [fig. 1; par. 0028 – “one of the storage devices 2 includes a NAND flash memory (hereinafter abbreviated as flash memory) 16 functioning as a non-volatile semiconductor memory”]; and a circuit configured to: reclaim, in response to storage access requests from the host system, a storage space occupied by the proof of space plot in the data storage medium [fig. 11; pars. 0054-0064 – The host may initiate garbage collection, which is a storage space request for clean blocks. Garbage collection is performed and the blocks are freed. Data of the proof of space plot previously stored in garbage collected blocks will be no longer available in those blocks. (“When the host 3 initiates the host-initiated garbage collection, in step 1110, the host 3 transmits a start host initiated garbage collection command (Start HIGC command) to storage device 2. The Start HIGC command contains a parameter HIGC_TIME, which specifies the maximum time during which the storage device 2 is allowed to perform the host-initiated garbage collection, in unit of milliseconds, and a parameter HIGC_SIZE, which is a minimum amount of free bocks which should be created through the host-initiated garbage collection.” … “In step 1210, the controller 10 updates the BMT 46, such that the target active block 46 is remapped as a free block 43 in the free block pool 430, and the process goes back to step 1120.”)]. However, Hashimoto does not specifically disclose, the circuit configured to: store, in the data storage medium, a proof of space plot [Hashimoto disclose storing data, but not specifically a proof of space plot file.]; In the same field of endeavor, Cohen et al. disclose, the circuit configured to: store, in the data storage medium, a proof of space plot [figs. 1, 4; par. 0032 – Plot files are stored on the space servers. (“More specifically, a space server in the distributed network can: generate a unique public-private key pair with which to generate plot files and/or sign newly generated blocks; allocate space an amount of drive storage (i.e., by generating plot files occupying space on disk); generate proofs-of-space in response to challenges received via the distributed network; and upon generating a valid proof-of-space to a challenge, generating a canonical block and a data block with which to extend the blockchain.”)]; It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hashimoto to include storing proof of space data, as taught by Cohen et al., in order to generate a blockchain while utilizing far less energy than other approaches. Claim 2 (as applied to claim 1 above): Hashimoto discloses, wherein the circuit is further configured to: receive, via the interface and from the host system, a storage space request [fig. 11; pars. 0054-0064 – The host may initiate garbage collection, which is a storage space request for clean blocks. Garbage collection is performed and the blocks are freed. Data of the proof of space plot previously stored in garbage collected blocks will be no longer available in those blocks. (“When the host 3 initiates the host-initiated garbage collection, in step 1110, the host 3 transmits a start host initiated garbage collection command (Start HIGC command) to storage device 2. The Start HIGC command contains a parameter HIGC_TIME, which specifies the maximum time during which the storage device 2 is allowed to perform the host-initiated garbage collection, in unit of milliseconds, and a parameter HIGC_SIZE, which is a minimum amount of free bocks which should be created through the host-initiated garbage collection.” … “In step 1210, the controller 10 updates the BMT 46, such that the target active block 46 is remapped as a free block 43 in the free block pool 430, and the process goes back to step 1120.”)]; and perform, in response to the storage space request, reallocation of a portion of the data storage medium storing a first portion of the proof of space plot to service the host system without deleting a second portion of the proof of space plot from the data storage medium [fig. 11; pars. 0054-0064 – The host may initiate garbage collection, which is a storage space request for clean blocks. Garbage collection is performed and the blocks are freed. Data of the proof of space plot previously stored in garbage collected blocks will be no longer available in those blocks. (“When the host 3 initiates the host-initiated garbage collection, in step 1110, the host 3 transmits a start host initiated garbage collection command (Start HIGC command) to storage device 2. The Start HIGC command contains a parameter HIGC_TIME, which specifies the maximum time during which the storage device 2 is allowed to perform the host-initiated garbage collection, in unit of milliseconds, and a parameter HIGC_SIZE, which is a minimum amount of free bocks which should be created through the host-initiated garbage collection.” … “In step 1210, the controller 10 updates the BMT 46, such that the target active block 46 is remapped as a free block 43 in the free block pool 430, and the process goes back to step 1120.”)]. Claim 4 (as applied to claim 2 above): Cohen et al. disclose, wherein the circuit is operable, after the reallocation of the portion of the data storage medium, to generate a response to a proof of space challenge based on the second portion of the proof of space plot [figs. 1,4; pars. 0013, 0035-0036 – The plot files are used in proof of space activities. (“More specifically, space servers can: store a plot file on disk; receive a challenge based on the most recent block in the block chain; retrieve a proof-of-space (i.e., a series of tuples from the plot file) that confirms the presence of the plot file on disk and is responsive to the challenge; and calculate a quality of the proof-of-space. Therefore, the space servers compete against all the space servers in the distributed network to retrieve a high-quality proof-of-space (i.e., higher than a threshold quality) in order to win the ability to add a block to the blockchain.”)]. Claim 10: Claim 10, directed to a method, is rejected for the same reasons set forth in the rejection of claim 1 above, mutatis mutandis. Claim 11 (as applied to claim 10 above): Claim 11, directed to a method, is rejected for the same reasons set forth in the rejection of claim 2 above, mutatis mutandis. Claim 13 (as applied to claim 11 above): Claim 13, directed to a method, is rejected for the same reasons set forth in the rejection of claim 4 above, mutatis mutandis. Claim 19: Claim 19, directed to a non-transitory computer readable storage medium, is rejected for the same reasons set forth in the rejection of claim 1 above, mutatis mutandis. Claim 20 (as applied to claim 19 above): Claim 20, directed to a non-transitory computer readable storage medium, is rejected for the same reasons set forth in the rejection of claim 4 above, mutatis mutandis. Claim(s) 6 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto (Pub. No. US 2017/0220292) in view of Cohen et al. (Pub. No. US 2021/0271667) as applied to claims 4 and 13 above, respectively, and further in view of Meir et al. (Pub. No. US 2012/0246391). Claim 6 (as applied to claim 4 above): Hashimoto discloses, wherein the circuit is configured to, prior to the reallocation of the portion of the data storage medium: retrieve the first portion of the proof of space plot [fig. 11; pars. 0054-0064 – Valid data is read to perform the garbage collection operation. (“In step 1140, the controller 10 selects one or more pages of a target active block 46 that contain valid data. Then, in step 1150, the controller 10 selects copies (transfers) the valid data from the selected pages of the target active block 46 to an input block 45 (44).”)]; However, Hashimoto and Cohen et al. do not specifically disclose, write the first portion of the proof of space plot to an auxiliary storage device. In the same field of endeavor, Meir et al. disclose, write the first portion of the proof of space plot to an auxiliary storage device [par. 0040 – Data may be written to a spare block. (“In some embodiments, each of the SLC and the MLC areas comprises a certain number of blocks 34 that serve as spare blocks. Spare blocks can be used for various purposes, such as for replacing blocks that become faulty ("bad blocks") and for over-provisioning used in compaction or "garbage collection" processes, as explained below.”)]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Hashimoto and Cohen et al. to include spare blocks, as taught by Meir et al., in order to allow bad blocks to be replaced in the memory. Claim 15 (as applied to claim 13 above): Claim 15, directed to a method, is rejected for the same reasons set forth in the rejection of claim 6 above, mutatis mutandis. Claim(s) 8 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto (Pub. No. US 2017/0220292) in view of Cohen et al. (Pub. No. US 2021/0271667) and Meir et al. (Pub. No. US 2012/0246391) as applied to claims 6 and 15 above, respectively, and further in view of Therene et al. (2020/0133898). Claim 8 (as applied to claim 6 above): Hashimoto, Cohen et al. and Meir et al. disclose all the limitations above but do not specifically disclose, wherein the circuit is configured to predict a storage space requirement of the host system and write the first portion of the proof of space plot to the auxiliary storage device in response to a prediction of the storage space requirement. In the same field of endeavor, Therene et al. disclose, wherein the circuit is configured to predict a storage space requirement of the host system and write the first portion of the proof of space plot to the auxiliary storage device in response to a prediction of the storage space requirement [par. 0067 – AI enabled garbage collection is performed. (“In contrast with conventional techniques, an example of predictive garbage collection enabled by the AI engine 132 and models 134 is shown at 610. In some aspects, a volume of storage media is configured with respective thresholds and free space to support predictive garbage collection 612 that may enable adaptive garbage collection operations that mitigate or avoid a reduction in host I/O performance (e.g., preventing host I/O throttling). Using the AI engine 132, the media access manager 130 may receive information relating to a predicted write burst 614 of a host system.”)]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Hashimoto, Cohen et al., and Meir et al. to include AI enabled garbage collection, as taught by Therene et al., in order to avoid a reduction in host I/O performance. Claim 17 (as applied to claim 15 above): Claim 17, directed to a method, is rejected for the same reasons set forth in the rejection of claim 8 above, mutatis mutandis. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LARRY T. MACKALL Primary Examiner Art Unit 2131 7 February 2026 /LARRY T MACKALL/Primary Examiner, Art Unit 2139
Read full office action

Prosecution Timeline

Aug 30, 2024
Application Filed
Jul 26, 2025
Non-Final Rejection — §103, §DP
Oct 29, 2025
Response Filed
Feb 07, 2026
Final Rejection — §103, §DP
Apr 09, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
94%
With Interview (+8.9%)
2y 7m
Median Time to Grant
Moderate
PTA Risk
Based on 779 resolved cases by this examiner. Grant probability derived from career allow rate.

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