DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending for examination. Claims 1, 14, and 20 are independent claims. This Office Action is Non-Final.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/17/2024 is in compliance with the provisions of 37 CFR 1.97, 37 CFR 1.98, and MPEP § 609. The Information Disclosure Statement has been placed in the application file and the information referred to therein has been considered as to the merits.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-5, 8-17, 19-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5, 8-12 of U.S. Patent No. 12,105,589 (reference patent). Although the Instant Application claims 1-5, 8-17, 19-20 and Patent No. 12,105,589 claims 1-5, 8-12 at issue are not identical, they are not patentably distinct from each other because, as shown in the table below, Instant Application claims 1-5, 8-17, 19-20 are anticipated by Patent No. 12,105,589 claims 1-5, 8-12.
Instant Application
18/821,203
U.S. Patent No. 12,105,589
1. A memory system, comprising:
one or more memory devices;
an associative processing memory; and
processing circuitry coupled with the one or more memory devices and the associative processing memory, the processing circuitry configured to cause the memory system to:
perform a computational operation on first data stored in first memory cells and second data stored in second memory cells;
perform the computational operation on a first set of one or more parity bits, for the first data, that is based at least in part on a quantity of the first memory cells storing a first logic value, and on a second set of one or more parity bits, for the second data, that is based at least in part on a quantity of the second memory cells storing the first logic value; and
determine whether third data representative of a result of the computational operation on the first data and the second data includes at least one error using fourth data representative of a result of the computational operation on the first set of one or more parity bits for the first data and the second set of one or more parity bits for the second data.
1. A method, comprising:
…
performing, by a memory plane of an associative processing memory, a computational operation on the first data stored in the first memory cells and the second data stored in the second memory cells;
performing, by the memory plane of the associative processing memory, the computational operation on a first set of one or more parity bits, for the first data, that is based at least in part on the first quantity of the first memory cells storing the first logic value, and on a second set of one or more parity bits, for the second data, that is based at least in part on the second quantity of the second memory cells storing the first logic value; and
writing, to third memory cells of the memory plane or a different memory plane, third data representative of a result of the computational operation on the first data and the second data and fourth data representative of a result of the computational operation on the first set of one or more parity bits for the first data and the second set of one or more parity bits for the second data.
2. The method of claim 1, further comprising:
determining that the third data has an error based at least in part on the fourth data; …
2. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
write, to third memory cells of a memory plane of the associative processing memory, the third data representative of the result of the computational operation on the first data and the second data and fourth data representative of the result of the computational operation on the first set of one or more parity bits for the first data and the second set of one or more parity bits for the second data.
1. A method, comprising:
…
performing, by a memory plane of an associative processing memory, …
writing, to third memory cells of the memory plane or a different memory plane, third data representative of a result of the computational operation on the first data and the second data and fourth data representative of a result of the computational operation on the first set of one or more parity bits for the first data and the second set of one or more parity bits for the second data.
3. The memory system of claim 1, wherein, to determine whether the third data includes an error, the processing circuitry is configured to cause the memory system to:
determine that the third data includes the at least one error based at least in part on the fourth data, wherein the processing circuitry is further configured to cause the memory system to:
correct the at least one error based at least in part on determining that the third data has the error.
2. The method of claim 1, further comprising:
determining that the third data has an error based at least in part on the fourth data; and
correcting the error based at least in part on determining that the third data has the error.
4. The memory system of claim 3, wherein the processing circuitry is further configured to cause the memory system to:
determine that a condition for performing error correction is satisfied, wherein the at least one error is corrected based at least in part on the condition for performing error correction being satisfied.
4. The method of claim 3, further comprising:
determining that a condition for performing error correction is satisfied, wherein the error is corrected based at least in part on the condition for performing error correction being satisfied.
5. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
determine that a condition for performing error detection is satisfied, wherein determining whether the third data includes the at least one error is based at least in part on the condition being satisfied.
3. The method of claim 2, further comprising:
determining that a condition for performing error detection is satisfied, wherein the determination that the third data has the error is based at least in part on the condition being satisfied.
8. The memory system of claim 7, wherein the processing circuitry is further configured to cause the memory system to:
receive the first operand, the second operand, the first set of one or more parity bits, and the second set of one or more parity bits; and
write the first data and the second data to a memory plane of the associative processing memory based at least in part on receiving the first operand, the second operand, the first set of one or more parity bits, and the second set of one or more parity bits.
Claims 1 and 5
9. The memory system of claim 1, wherein the first data is representative of a set of contiguous bits of a first operand and the second data is representative of a set of contiguous bits of a second operand, the first operand and the second operand associated with the computational operation, and wherein the processing circuitry is further configured to cause the memory system to:
perform the computational operation on fifth data and sixth data stored in a second memory plane of the associative processing memory, the fifth data representative of a second set of contiguous bits of the first operand, and the sixth data representative of a second set of contiguous bits of the second operand; and
perform the computational operation on seventh data and eighth data stored in the second memory plane, the seventh data representative of a third set of one or more parity bits for the fifth data, and the eighth data representative of a fourth set of one or more parity bits for the sixth data.
Claims 1 and 9
10. The memory system of claim 9, wherein the processing circuitry is further configured to cause the memory system to:
determine that ninth data representative of a result of the computational operation on the fifth data and the sixth data has an error based at least in part on tenth data representative of a result of the computational operation on the seventh data and the eighth data.
Claim 8
11. The memory system of claim 9, wherein the computational operation on the first data and the second data is based at least in part on a first value for an arithmetic output bit, and wherein the computational operation on the fifth data and the sixth data is based at least in part on a second value for the arithmetic output bit.
Claim 10
12. The memory system of claim 9, wherein the processing circuitry is further configured to cause the memory system to:
determine that the third data has an error based at least in part on the fourth data;
determine that ninth data representative of a result of the computational operation on the fifth data and the sixth data is error-free based at least in part on tenth data representative of a result of the computational operation on the seventh data and the eighth data; and
selecting the ninth data for a second computational operation based at least in part on the third data having the error and the ninth data being error-free.
Claim 11
13. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
sense a set of content-addressable memory cells that store a truth table associated with the computational operation, wherein the computational operation on the first data and the second data is performed based at least in part on sensing the set of content-addressable memory cells that store the truth table, and wherein the computational operation on the first set of one or more parity bits and the second set of one or more parity bits is performed based at least in part on sensing the set of content-addressable memory cells that store the truth table.
Claim 12
14. A method by a memory system, comprising:
performing a computational operation on first data stored in first memory cells and second data stored in second memory cells;
performing the computational operation on a first set of one or more parity bits, for the first data, that is based at least in part on a quantity of the first memory cells storing a first logic value, and on a second set of one or more parity bits, for the second data, that is based at least in part on a quantity of the second memory cells storing the first logic value; and
determining whether third data representative of a result of the computational operation on the first data and the second data includes at least one error using fourth data representative of a result of the computational operation on the first set of one or more parity bits for the first data and the second set of one or more parity bits for the second data.
1. A method, comprising:
…
performing, by a memory plane of an associative processing memory, a computational operation on the first data stored in the first memory cells and the second data stored in the second memory cells;
performing, by the memory plane of the associative processing memory, the computational operation on a first set of one or more parity bits, for the first data, that is based at least in part on the first quantity of the first memory cells storing the first logic value, and on a second set of one or more parity bits, for the second data, that is based at least in part on the second quantity of the second memory cells storing the first logic value; and
writing, to third memory cells of the memory plane or a different memory plane, third data representative of a result of the computational operation on the first data and the second data and fourth data representative of a result of the computational operation on the first set of one or more parity bits for the first data and the second set of one or more parity bits for the second data.
2. The method of claim 1, further comprising:
determining that the third data has an error based at least in part on the fourth data; …
15. The method of claim 14, further comprising:
write, to third memory cells of a memory plane of an associative processing memory, the third data representative of the result of the computational operation on the first data and the second data and fourth data representative of the result of the computational operation on the first set of one or more parity bits for the first data and the second set of one or more parity bits for the second data.
1. A method, comprising:
…
performing, by a memory plane of an associative processing memory, …
writing, to third memory cells of the memory plane or a different memory plane, third data representative of a result of the computational operation on the first data and the second data and fourth data representative of a result of the computational operation on the first set of one or more parity bits for the first data and the second set of one or more parity bits for the second data.
16. The method of claim 14, wherein determining whether the third data includes an error comprises:
determining that the third data includes the at least one error based at least in part on the fourth data, the method further comprising:
determining that a condition for performing error correction is satisfied; and
correcting the at least one error based at least in part on determining that the third data has the error and based at least in part on the condition for performing error correction being satisfied.
2. The method of claim 1, further comprising:
determining that the third data has an error based at least in part on the fourth data; and
correcting the error based at least in part on determining that the third data has the error.
4. The method of claim 3, further comprising:
determining that a condition for performing error correction is satisfied, wherein the error is corrected based at least in part on the condition for performing error correction being satisfied.
17. The method of claim 14, further comprising:
determining that a condition for performing error detection is satisfied, wherein determining whether the third data includes the at least one error is based at least in part on the condition being satisfied.
3. The method of claim 2, further comprising:
determining that a condition for performing error detection is satisfied, wherein the determination that the third data has the error is based at least in part on the condition being satisfied.
19. The method of claim 14, the method further comprising:
receiving a first operand, a second operand, the first set of one or more parity bits, and the second set of one or more parity bits, wherein the first data is representative of a set of contiguous bits of the first operand and the second data is representative of a set of contiguous bits of the second operand, the first operand and the second operand associated with the computational operation; and
writing the first data and the second data to a memory plane of an associative processing memory.
Claims 1 and 5
20. A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to:
perform a computational operation on first data stored in first memory cells and second data stored in second memory cells;
perform the computational operation on a first set of one or more parity bits, for the first data, that is based at least in part on a quantity of the first memory cells storing a first logic value, and on a second set of one or more parity bits, for the second data, that is based at least in part on a quantity of the second memory cells storing the first logic value; and
determine whether third data representative of a result of the computational operation on the first data and the second data includes at least one error using fourth data representative of a result of the computational operation on the first set of one or more parity bits for the first data and the second set of one or more parity bits for the second data.
1. A method, comprising:
…
performing, by a memory plane of an associative processing memory, a computational operation on the first data stored in the first memory cells and the second data stored in the second memory cells;
performing, by the memory plane of the associative processing memory, the computational operation on a first set of one or more parity bits, for the first data, that is based at least in part on the first quantity of the first memory cells storing the first logic value, and on a second set of one or more parity bits, for the second data, that is based at least in part on the second quantity of the second memory cells storing the first logic value; and
writing, to third memory cells of the memory plane or a different memory plane, third data representative of a result of the computational operation on the first data and the second data and fourth data representative of a result of the computational operation on the first set of one or more parity bits for the first data and the second set of one or more parity bits for the second data.
2. The method of claim 1, further comprising:
determining that the third data has an error based at least in part on the fourth data; …
With regards to double patenting of claims 1-5, 8-17, 19-20 of the Instant Application, claims 1-5, 8-12 of U.S. Patent No. 12,105,589 is in essence a “species” of the generic invention of Instant Application claims 1-5, 8-17, 19-20. It has been held that a generic invention is “anticipated” by a “species” within the scope of the generic invention. See In re Goodman, 29 USPQ2d 2010 (Fed. Cir. 1993) and MPEP 806.04(i).
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to (an) abstract idea(s) without significantly more.
Claims 1, 14, and 20 recite:
perform a computational operation on first data stored in first memory cells and second data stored in second memory cells;
perform the computational operation on a first set of one or more parity bits, for the first data, that is based at least in part on a quantity of the first memory cells storing a first logic value, and on a second set of one or more parity bits, for the second data, that is based at least in part on a quantity of the second memory cells storing the first logic value; and
determine whether third data representative of a result of the computational operation on the first data and the second data includes at least one error using fourth data representative of a result of the computational operation on the first set of one or more parity bits for the first data and the second set of one or more parity bits for the second data.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes:
Claim 1 is a machine.
Claim 14 is a method.
Claim 20 is an article of manufacture.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The limitations of ‘perform a computational operation’ in # 1 and 2 above and “determine whether third data” in #3, as claimed and under broadest reasonable interpretation (BRI), are mental processes that covers performance of the limitation in the mind and mathematical concepts. For example, “perform” in the context of this claim encompasses a person performing an arithmetic or logic operation on data. Furthermore, “determine” in the context of this claim encompasses a person making a judgement about data.
Step 2A, Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The ‘first memory cells storing a first logic value’ and ‘second memory cells storing the first logic value’ limitations in # 2 above, as claimed and under BRI, is an additional element that is insignificant extra-solution activity. For example, “storing” in the context of this claim encompasses mere data gathering. See MPEP 2106.05(g).
Additionally, one or more of the claims recite the following additional elements:
a memory system (Claims 1, 14),
memory devices (Claim 1),
associative processing memory (Claims 1, 15),
processing circuitry (Claims 1, 20),
memory cells (Claims 1, 14, 20), and
a memory plane (Claims 2, 15).
These additional elements are recited at a high level of generality (i.e. as generic computer components) such that they amount to no more than components comprising mere instructions to apply the exception. Accordingly, these additional elements do not integrate the abstract idea(s) into a practical application because they do not impose any meaningful limits on practicing the abstract idea(s). See MPEP 2106.05(f).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
As discussed above with respect to integration of the abstract idea(s) into a practical application, the aforementioned additional elements amount to no more than components comprising mere instructions to apply the exception. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept.
Additionally, with regards to # 1-3 above, per MPEP 2106.05(d)(Il), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
Claims 2 and 15 merely further describes generic storing and retrieving information in memory of Claim 1 under Step 2A, Prong 2 and Step 2B, see analysis above.
Claims 3 and 16 recite:
wherein, to determine whether the third data includes an error, the processing circuitry is configured to cause the memory system to:
4. determine that the third data includes the at least one error based at least in part on the fourth data, wherein the processing circuitry is further configured to cause the memory system to:
5. correct the at least one error based at least in part on determining that the third data has the error.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes: an apparatus.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘determine’ limitation in # 4 above and ‘correct’ limitation in #5 above, as claimed and under broadest reasonable interpretation (BRI), are mental processes that covers performance of the limitation in the mind. For example, “determine” in the context of this claim encompasses the person making an observation about data and ‘correct’ is determining the correct data.
Claims 4 and 16 recite:
wherein the processing circuitry is further configured to cause the memory system to:
6. determine that a condition for performing error correction is satisfied, wherein the at least one error is corrected based at least in part on the condition for performing error correction being satisfied.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes: an apparatus.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘determine’ limitation in # 6 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. For example, “determine” in the context of this claim encompasses the person making an observation about data.
Claims 5 and 17 recite:
wherein the processing circuitry is further configured to cause the memory system to:
6. determine that a condition for performing error detection is satisfied, wherein determining whether the third data includes the at least one error is based at least in part on the condition being satisfied.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes: an apparatus.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘determine’ limitation in # 7 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. For example, “determine” in the context of this claim encompasses the person making an observation about data.
Claims 6 and 18 merely further describes generic storing and retrieving information in memory of Claim 1 under Step 2A, Prong 2 and Step 2B, see analysis above.
Claims 7 and 19 recite:
8. wherein the first data is representative of a set of contiguous bits of a first operand and the second data is representative of a set of contiguous bits of a second operand, the first operand and the second operand associated with the computational operation, and wherein, to perform the computational operation on the first data and the second data, the processing circuitry is further configured to cause the memory system to:
9. compare one or more first operand bits associated with the first operand and one or more second operand bits associated with the second operand with one or more entries of a truth table.
Claim 7, limitation 8 merely further describes the claimed first data and second data of Claim 1.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes: an apparatus.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘compare’ limitation in # 9 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. For example, “compare” in the context of this claim encompasses the person making comparisons and observations about data.
Claims 8 and 19 merely further describes generic storing and retrieving information in memory of Claim 7 under Step 2A, Prong 2 and Step 2B, see analysis above.
Claim 9 recites:
10. wherein the first data is representative of a set of contiguous bits of a first operand and the second data is representative of a set of contiguous bits of a second operand, the first operand and the second operand associated with the computational operation, and wherein the processing circuitry is further configured to cause the memory system to:
11. perform the computational operation on fifth data and sixth data stored in a second memory plane of the associative processing memory, the fifth data representative of a second set of contiguous bits of the first operand, and the sixth data representative of a second set of contiguous bits of the second operand; and
12. perform the computational operation on seventh data and eighth data stored in the second memory plane, the seventh data representative of a third set of one or more parity bits for the fifth data, and the eighth data representative of a fourth set of one or more parity bits for the sixth data.
Claim 9, limitation 10 merely further describes the claimed first data and second data of Claim 1.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes: an apparatus.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘perform’ limitations in # 11 and 12 above, as claimed and under broadest reasonable interpretation (BRI), are mental processes that cover performance of the limitation in the mind. For example, “perform” in the context of this claim encompasses a person performing an arithmetic or logic operation on data.
Claim 10 recites:
wherein the processing circuitry is further configured to cause the memory system to:
13. determine that ninth data representative of a result of the computational operation on the fifth data and the sixth data has an error based at least in part on tenth data representative of a result of the computational operation on the seventh data and the eighth data.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes: an apparatus.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘determine’ limitation in # 13 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. For example, “determine” in the context of this claim encompasses the person making an observation about data.
Claim 11 merely further describes the claimed arithmetic output bit of Claim 9.
Claim 12 recites:
wherein the processing circuitry is further configured to cause the memory system to:
14. determine that the third data has an error based at least in part on the fourth data;
15. determine that ninth data representative of a result of the computational operation on the fifth data and the sixth data is error-free based at least in part on tenth data representative of a result of the computational operation on the seventh data and the eighth data; and
16. selecting the ninth data for a second computational operation based at least in part on the third data having the error and the ninth data being error-free.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes: an apparatus.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘determine’ limitations in # 14, 15 above and ‘selecting’ limitation in #16, as claimed and under broadest reasonable interpretation (BRI), are mental processes that cover performance of the limitation in the mind. For example, “determine” in the context of this claim encompasses the person making an observation about data.
Claim 6 merely further describes generic storing and retrieving information in memory of Claim 1 under Step 2A, Prong 2 and Step 2B, see analysis above.
For at least the reasoning provided above, Claims 1-20 are patent ineligible.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, 14-17, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Petersson (U.S. Patent No. 10,078,565, cited in IDS), hereinafter Peters in view of Wikipedia Article (Non-Patent Literature “Function (computer programming)”, published Dec. 30, 2021, retrieved from https://en.wikipedia.org/w/index.php?title=Function_(computer_programming)&oldid=1062701489 on Nov. 21, 2023), hereinafter NPL Function.
Regarding claim 1, Peters teaches (in bold) a method, comprising:
A memory system (Peters, Fig. 1, col. 5, lines 58-67 processing circuit, error detection circuit, control circuit is implemented in “programmable resources of a programmable IC…writing program data to a configuration memory” that may be memory of a memory system), comprising:
one or more memory devices (Peters, Fig. 1, col. 5, lines 58-67 processing circuit, error detection circuit, control circuit is implemented in memory, see also Fig. 8, on-chip memory 822);
an associative processing memory (Applicant’s originally filed specification in paragraph 21 describes associative processing memory as accelerator or high-speed processor, see MPEP 2111.01(V). Peters, Figs. 1, 2 col. 4, lines 1-67 and col. 5, lines 1-10 teaches error detection circuit, control circuit); and
processing circuitry coupled with the one or more memory devices and the associative processing memory (Peters, Figs. 1-2 processing circuitry 110, 112, 114 connects to other circuits such as APM implemented on memory devices comprising Control circuit and Error Detection Circuit 230), the processing circuitry configured to cause the memory system to:
perform a computational operation on first data stored in first memory cells and second data stored in second memory cells (Peters, Fig. 1, col. 4 data In input to Processing circuit 1 110 (i.e. first data) and data In input to Processing circuit 1 110 (i.e. second data). Fig. 8, col. 8, lines 45-48 teach processing circuits 812, 814, 816, 818 shown in Peters Fig. 1 that include “on-chip memory”. Furthermore, Col. 8 lines 49-67 and col. 9, lines 1-11 teach processors 812-818 access programmable resources 832 that include memory cells. Col 9, lines 1-5 teaches multiple memory cells that are different in either processors 812-814 or programmable resources 832 “collective states of the individual memory cells”. Col. 9, lines 27-30 teaches “the processing sub-system 810 and the programmable logic sub-system 830 may also read or write to memory locations [i.e. first memory cells, second memory cells] of an on-chip memory 822 or off-chip memory (not shown) via memory controller 821.” Flip flop or latch made up of memory cells to store data is taught in col. 1, lines 43-51.);
perform the computational operation on a first set of one or more parity bits, for the first data (Examiner under BRI interprets “parity bits” as defined in originally filed specification as “Parity bits may also be referred to as error detection bits, error correction bits, or other suitable terminology.” Peters, Fig. 8, Col. 9, lines 27-44 teaches memory has 16 bit or 32 bit with ECC (Error Correcting Code) that includes parity bits. Fig. 1 data In input to Processing circuit 2 112 includes parity bits for first data), that is based at least in part on a quantity of the first memory cells storing a first logic value, and on a second set of one or more parity bits, for the second data (Peters, Fig. 8, Col. 9, lines 27-44 teaches memory has 16 bit or 32 bit with ECC (Error Correcting Code) that includes parity bits. Fig. 1 data In input to Processing circuit 2 112 includes parity bits for second data), that is based at least in part on a quantity of the second memory cells storing the first logic value; and
determine whether third data representative of a result of the computational operation on the first data and the second data includes at least one error (The Examiner under BRI interprets “third data” as the result of computational operation on the first data and the second data as recited in element of claim 1, lines 7-8 “perform a computational operation …”. Peters, Fig. 1, col. 4, lines 5-22, value P1 output by Processing circuit 1, col. 4, lines 63-67, col. 5, lines 1-11, see also Fig. 6. P1 output [i.e. third data] is different from first data and second data inputs to processing circuit as P1 is result of computation operation in processing circuit. Peters teaches in Fig. 2 that majority voter P1 third data and P2 fourth data is input to Majority voters 240 and Fault locators 260 in Error Detection Circuit 120, see description of Fig. 2 in col. 4, lines 57-67, col. 5) using fourth data representative of a result of the computational operation on the first set of one or more parity bits for the first data and the second set of one or more parity bits for the second data (Examiner under BRI interprets “parity bits” as defined in originally filed specification as “Parity bits may also be referred to as error detection bits, error correction bits, or other suitable terminology.” Peters, Fig. 1, col. 4, lines 5-22, value P2 output [i.e. fourth data] by Processing circuit 2, col. 4, lines 63-67, col. 5, lines 1-11, see also Fig. 6. Peters in Fig. 8, Col. 9, lines 27-44 teaches memory has 16 bit or 32 bit data with ECC (Error Correcting Code) that includes parity bits. Fig. 1 data In input to Processing circuit 2 112 includes parity bits for first data. Fig. 1 data In input to Processing circuit 2 112 includes parity bits for second data).
Peters does not distinctly disclose perform the computational operation that is based at least in part on a quantity of the first memory cells storing a first logic value, that is based at least in part on a quantity of the second memory cells storing the first logic value. NPL Function, in the same field of endeavor of processing circuitry performing computational operations on data in memory (see NPL Function page 2 “modifying data structures in computer memory” and example function/subroutine computation operations on page 10), teaches perform a computational operation (NPL Function, page 10 “change the sign of each element of a two-dimensional array” and change_sign subroutine is computational operation that has function “declare array2 (16,16) float” which has same first data In=16 and second data In=16 and executed in Processing circuit) that is based at least in part on a quantity of the first memory cells storing a first logic value (NPL Function, page 10, first logic value of decimal 16 in binary is 10000, thus for 8 bit memory cells (a byte), 5 bits of the 8 bits store the first logic value [i.e. quantity of the first memory cells] and other 3 bits are unused), that is based at least in part on a quantity of the second memory cells storing the first logic value (NPL Function, page 10, first logic value of decimal 16 in binary is 10000, thus for 8 bit memory cells (a byte), 5 bits of the 8 bits store the first logic value [i.e. quantity of the second memory cells] and other 3 bits are unused).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Peters to incorporate the teachings of NPL Function and provide for same computational operation on data and parity of the data to determine errors because judicious and repetitive use of the same computational operation function increases efficiency and reduces the cost of developing and maintaining a large program while increasing its quality and reliability (NPL Function, page 1, paragraph 4).
Regarding claim 2, Peters as modified by NPL Function teaches all of the limitations of claim 1 as cited above and Peters further teaches:
write, to third memory cells of a memory plane of the associative processing memory, the third data representative of the result of the computational operation on the first data and the second data (Peters, Fig. 1, col. 4, lines 5-22, value P1 output by Processing circuit 1, col. 4, lines 63-67, col. 5, lines 1-11, see also Fig. 6) and fourth data representative of the result of the computational operation on the first set of one or more parity bits for the first data and the second set of one or more parity bits for the second data (Peters, Fig. 1, col. 4, lines 5-22, value P2 output by Processing circuit 2, col. 4, lines 63-67, col. 5, lines 1-11, see also Fig. 6).
Regarding claim 3, Peters as modified by NPL Function teaches all of the limitations of claim 1 as cited above and Peters further teaches wherein, to determine whether the third data includes an error, the processing circuitry is configured to cause the memory system to:
determine that the third data includes the at least one error based at least in part on the fourth data (Peters, Fig. 1, col. 4, lines 5-22, value P1 output by Processing circuit 1, col. 4, lines 63-67, col. 5, lines 1-11, see also Fig. 6. P1 output [i.e. third data] is result of computation operation in processing circuit of first data and second data. Peters teaches in Fig. 2 that majority voter P1 third data and P2 fourth data [i.e. fourth data is computational operation perform on first data parity bits and second data parity bits, see claim mapping above] is input to Majority voters 240 and Fault locators 260 in Error Detection Circuit 120, see description of Fig. 2 in col. 4, lines 57-67, col. 5 “error detection circuit 230 is configured to detect … errors in the processing circuits 210, 212 …based on comparison of signals P1, P2 …output by the processing circuits.” See also description of fault locator circuits 260 in col. 5, lines 12-30 that teaches generating signal P1-P2 indicating if P1 and P2 are matched or mismatched), wherein the processing circuitry is further configured to cause the memory system to:
correct the at least one error based at least in part on determining that the third data has the error (Peters, Fig. 2, col. 5, lines 1-11 “If one of the signals P1, P2, P3 is in error, the output value of the majority voter circuit is still equal to the correct error-free value.” If P1 output [i.e. third data] has the error, it will be corrected to error-free value as taught by Peters in Fig. 2, col. 5, lines 1-11).
Regarding claim 4, Peters as modified by NPL Function teaches all of the limitations of claim 3 as cited above and Peters further teaches wherein the processing circuitry is further configured to cause the memory system to:
determine that a condition for performing error correction is satisfied (Peters, Fig. 4, block 412, col. 6, lines 49-67 teaches “At block 412, the processing circuits are monitored for errors (e.g., by error detection circuit 120) until an error is detected at decision block 414.”), wherein the at least one error is corrected based at least in part on the condition for performing error correction being satisfied (Peters, Fig. 4, block 416 Trigger power-on-reset or block 418 Disable non-functioning processing circuits, col. 6, lines 60-67 and col. 7, lines 1-9).
Regarding claim 5, Peters as modified by NPL Function teaches all of the limitations of claim 1 as cited above and Peters further teaches wherein the processing circuitry is further configured to cause the memory system to:
determine that a condition for performing error detection is satisfied (Peters, Fig. 4, block 412, col. 6, lines 49-67 teaches “At block 412, the processing circuits are monitored for errors (e.g., by error detection circuit 120) until an error is detected at decision block 414.”), wherein determining whether the third data includes the at least one error is based at least in part on the condition being satisfied (Peters, Fig. 4, Non-fatal error or Fatal error detected so condition is satisfied and Fig. 2 shows P1 that is third data is input to Majority voters 240 after nonfatal or fatal error detected col. 4, lines 57-67 and col. 5).
Regarding claim 7, Peters as modified by NPL Function teaches all of the limitations of claim 1 as cited above and Peters further teaches (in bold) wherein the first data is representative of a set of contiguous bits of a first operand (Peters, Fig. 1 data In input is a variable/multiple bytes/multiple words that are contiguous bits, first operand In input to Processing circuit 1 110) and the second data is representative of a set of contiguous bits of a second operand (Peters, Fig. 1 data In input is a variable/multiple bytes/multiple words that are contiguous bits, second operand In input to Processing circuit 1 110), the first operand and the second operand associated with the computational operation and wherein, to perform the computational operation on the first data and the second data, the processing circuitry is further configured to cause the memory system to: compare one or more first operand bits associated with the first operand and one or more second operand bits associated with the second operand with one or more entries of a truth table.
Peters does not distinctly disclose the first operand and the second operand associated with the computational operation: compare one or more first operand bits associated with the first operand and one or more second operand bits associated with the second operand with one or more entries of a truth table. NPL Function, in the same field of endeavor, teaches the first operand and the second operand associated with the computational operation (NPL Function, page 10 “change the sign of each element of a two-dimensional array” and change_sign subroutine is computational operation that has function “declare array2 (16,16) float” which has same first data In=16 and second data In=16 and executed in Processing circuit), and wherein, to perform the computational operation on the first data and the second data, the processing circuitry is further configured to cause the memory system to: compare one or more first operand bits associated with the first operand and one or more second operand bits associated with the second operand with one or more entries of a truth table (NPL Function, page 10 inversion truth table determined and implemented in code so array=-array. Page 10 teaches change_sign: procedure (array). Inversion of sign requires comparison of logic bits in binary 10000, decimal 16).
The motivation to combine for claim 7 is the same as the motivation to combine for claim 1.
Regarding claim 8, Peters as modified by NPL Function teaches all of the limitations of claim 7 as cited above and Peters further teaches receive the first operand, the second operand, the first set of one or more parity bits, and the second set of one or more parity bits (Peters, Fig. 8, Col. 9, lines 27-44 teaches memory has 16 bit or 32 bit with ECC (Error Correcting Code) that includes parity bits. Fig. 1 data In input to Processing circuit 1 110 includes parity bits for first data of first operand. Fig. 1 data In input to Processing circuit 1 110 includes parity bits for second data of second operand); and
write the first data and the second data to a memory plane of the associative processing memory based at least in part on receiving the first operand, the second operand, the first set of one or more parity bits, and the second set of one or more parity bits (Peters, Fig. 1, col. 5, lines 58-67 processing circuit is implemented in programmable resources of a programmable IC that may be memory, data with ECC parity bits is processed and written to memory “writing program data to a configuration memory”).
Regarding claim 14, Peters teaches (in bold) a method, comprising:
A method by a memory system (Peters, Fig. 1, col. 5, lines 58-67 processing circuit, error detection circuit, control circuit is implemented in “programmable resources of a programmable IC…writing program data to a configuration memory” that may be memory of a memory system), comprising:
performing a computational operation on first data stored in first memory cells and second data stored in second memory cells (Peters, Fig. 1, col. 4 data In input to Processing circuit 1 110 (i.e. first data) and data In input to Processing circuit 1 110 (i.e. second data). Fig. 8, col. 8, lines 45-48 teach processing circuits 812, 814, 816, 818 shown in Peters Fig. 1 that include “on-chip memory”. Furthermore, Col. 8 lines 49-67 and col. 9, lines 1-11 teach processors 812-818 access programmable resources 832 that include memory cells. Col 9, lines 1-5 teaches multiple memory cells that are different in either processors 812-814 or programmable resources 832 “collective states of the individual memory cells”. Col. 9, lines 27-30 teaches “the processing sub-system 810 and the programmable logic sub-system 830 may also read or write to memory locations [i.e. first memory cells, second memory cells] of an on-chip memory 822 or off-chip memory (not shown) via memory controller 821.” Flip flop or latch made up of memory cells to store data is taught in col. 1, lines 43-51.);
performing the computational operation on a first set of one or more parity bits, for the first data (Examiner under BRI interprets “parity bits” as defined in originally filed specification as “Parity bits may also be referred to as error detection bits, error correction bits, or other suitable terminology.” Peters, Fig. 8, Col. 9, lines 27-44 teaches memory has 16 bit or 32 bit with ECC (Error Correcting Code) that includes parity bits. Fig. 1 data In input to Processing circuit 2 112 includes parity bits for first data), that is based at least in part on a quantity of the first memory cells storing a first logic value, and on a second set of one or more parity bits, for the second data (Peters, Fig. 8, Col. 9, lines 27-44 teaches memory has 16 bit or 32 bit with ECC (Error Correcting Code) that includes parity bits. Fig. 1 data In input to Processing circuit 2 112 includes parity bits for second data), that is based at least in part on a quantity of the second memory cells storing the first logic value; and
determining whether third data representative of a result of the computational operation on the first data and the second data includes at least one error (The Examiner under BRI interprets “third data” as the result of computational operation on the first data and the second data as recited in element of claim 1, lines 7-8 “perform a computational operation …”. Peters, Fig. 1, col. 4, lines 5-22, value P1 output by Processing circuit 1, col. 4, lines 63-67, col. 5, lines 1-11, see also Fig. 6. P1 output [i.e. third data] is different from first data and second data inputs to processing circuit as P1 is result of computation operation in processing circuit. Peters teaches in Fig. 2 that majority voter P1 third data and P2 fourth data is input to Majority voters 240 and Fault locators 260 in Error Detection Circuit 120, see description of Fig. 2 in col. 4, lines 57-67, col. 5) using fourth data representative of a result of the computational operation on the first set of one or more parity bits for the first data and the second set of one or more parity bits for the second data (Examiner under BRI interprets “parity bits” as defined in originally filed specification as “Parity bits may also be referred to as error detection bits, error correction bits, or other suitable terminology.” Peters, Fig. 1, col. 4, lines 5-22, value P2 output [i.e. fourth data] by Processing circuit 2, col. 4, lines 63-67, col. 5, lines 1-11, see also Fig. 6. Peters in Fig. 8, Col. 9, lines 27-44 teaches memory has 16 bit or 32 bit with ECC (Error Correcting Code) that includes parity bits. Fig. 1 data In input to Processing circuit 2 112 includes parity bits for first data. Fig. 1 data In input to Processing circuit 2 112 includes parity bits for second data).
Peters does not distinctly disclose perform the computational operation that is based at least in part on a quantity of the first memory cells storing a first logic value, that is based at least in part on a quantity of the second memory cells storing the first logic value. NPL Function, in the same field of endeavor of processing circuitry performing computational operations on data in memory (see NPL Function page 2 “modifying data structures in computer memory” and example function/subroutine computation operations on page 10), teaches perform a computational operation (NPL Function, page 10 “change the sign of each element of a two-dimensional array” and change_sign subroutine is computational operation that has function “declare array2 (16,16) float” which has same first data In=16 and second data In=16 and executed in Processing circuit) that is based at least in part on a quantity of the first memory cells storing a first logic value (NPL Function, page 10, first logic value of decimal 16 in binary is 10000, thus for 8 bit memory cells (a byte), 5 bits of the 8 bits store the first logic value [i.e. quantity of the first memory cells] and other 3 bits are unused), that is based at least in part on a quantity of the second memory cells storing the first logic value (NPL Function, page 10, first logic value of decimal 16 in binary is 10000, thus for 8 bit memory cells (a byte), 5 bits of the 8 bits store the first logic value [i.e. quantity of the second memory cells] and other 3 bits are unused).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Peters to incorporate the teachings of NPL Function and provide for same computational operation on data and parity of the data to determine errors because judicious and repetitive use of the same computational operation function increases efficiency and reduces the cost of developing and maintaining a large program while increasing its quality and reliability (NPL Function, page 1, paragraph 4).
Claims 15-17 and 19 the method that implements the system of claims 2-5 and 7-8, respectively, are rejected on the same grounds as claims 2-5 and 7-8, respectively.
Regarding claim 20, Peters teaches (in bold) a method, comprising:
A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device (Peters, Figs. 1-2 processing circuitry 110, 112, 114 connects to other circuits such as Control circuit and Error Detection Circuit 230), cause the electronic device to:
perform a computational operation on first data stored in first memory cells and second data stored in second memory cells (Peters, Fig. 1, col. 4 data In input to Processing circuit 1 110 (i.e. first data) and data In input to Processing circuit 1 110 (i.e. second data). Fig. 8, col. 8, lines 45-48 teach processing circuits 812, 814, 816, 818 shown in Peters Fig. 1 that include “on-chip memory”. Furthermore, Col. 8 lines 49-67 and col. 9, lines 1-11 teach processors 812-818 access programmable resources 832 that include memory cells. Col 9, lines 1-5 teaches multiple memory cells that are different in either processors 812-814 or programmable resources 832 “collective states of the individual memory cells”. Col. 9, lines 27-30 teaches “the processing sub-system 810 and the programmable logic sub-system 830 may also read or write to memory locations [i.e. first memory cells, second memory cells] of an on-chip memory 822 or off-chip memory (not shown) via memory controller 821.” Flip flop or latch made up of memory cells to store data is taught in col. 1, lines 43-51.);
perform the computational operation on a first set of one or more parity bits, for the first data (Examiner under BRI interprets “parity bits” as defined in originally filed specification as “Parity bits may also be referred to as error detection bits, error correction bits, or other suitable terminology.” Peters, Fig. 8, Col. 9, lines 27-44 teaches memory has 16 bit or 32 bit with ECC (Error Correcting Code) that includes parity bits. Fig. 1 data In input to Processing circuit 2 112 includes parity bits for first data), that is based at least in part on a quantity of the first memory cells storing a first logic value, and on a second set of one or more parity bits, for the second data (Peters, Fig. 8, Col. 9, lines 27-44 teaches memory has 16 bit or 32 bit with ECC (Error Correcting Code) that includes parity bits. Fig. 1 data In input to Processing circuit 2 112 includes parity bits for second data), that is based at least in part on a quantity of the second memory cells storing the first logic value; and
determine whether third data representative of a result of the computational operation on the first data and the second data includes at least one error (The Examiner under BRI interprets “third data” as the result of computational operation on the first data and the second data as recited in element of claim 1, lines 7-8 “perform a computational operation …”. Peters, Fig. 1, col. 4, lines 5-22, value P1 output by Processing circuit 1, col. 4, lines 63-67, col. 5, lines 1-11, see also Fig. 6. P1 output [i.e. third data] is different from first data and second data inputs to processing circuit as P1 is result of computation operation in processing circuit. Peters teaches in Fig. 2 that majority voter P1 third data and P2 fourth data is input to Majority voters 240 and Fault locators 260 in Error Detection Circuit 120, see description of Fig. 2 in col. 4, lines 57-67, col. 5) using fourth data representative of a result of the computational operation on the first set of one or more parity bits for the first data and the second set of one or more parity bits for the second data (Examiner under BRI interprets “parity bits” as defined in originally filed specification as “Parity bits may also be referred to as error detection bits, error correction bits, or other suitable terminology.” Peters, Fig. 1, col. 4, lines 5-22, value P2 output [i.e. fourth data] by Processing circuit 2, col. 4, lines 63-67, col. 5, lines 1-11, see also Fig. 6. Peters in Fig. 8, Col. 9, lines 27-44 teaches memory has 16 bit or 32 bit with ECC (Error Correcting Code) that includes parity bits. Fig. 1 data In input to Processing circuit 2 112 includes parity bits for first data. Fig. 1 data In input to Processing circuit 2 112 includes parity bits for second data).
Peters does not distinctly disclose perform the computational operation that is based at least in part on a quantity of the first memory cells storing a first logic value, that is based at least in part on a quantity of the second memory cells storing the first logic value. NPL Function, in the same field of endeavor of processing circuitry performing computational operations on data in memory (see NPL Function page 2 “modifying data structures in computer memory” and example function/subroutine computation operations on page 10), teaches perform a computational operation (NPL Function, page 10 “change the sign of each element of a two-dimensional array” and change_sign subroutine is computational operation that has function “declare array2 (16,16) float” which has same first data In=16 and second data In=16 and executed in Processing circuit) that is based at least in part on a quantity of the first memory cells storing a first logic value (NPL Function, page 10, first logic value of decimal 16 in binary is 10000, thus for 8 bit memory cells (a byte), 5 bits of the 8 bits store the first logic value [i.e. quantity of the first memory cells] and other 3 bits are unused), that is based at least in part on a quantity of the second memory cells storing the first logic value (NPL Function, page 10, first logic value of decimal 16 in binary is 10000, thus for 8 bit memory cells (a byte), 5 bits of the 8 bits store the first logic value [i.e. quantity of the second memory cells] and other 3 bits are unused).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Peters to incorporate the teachings of NPL Function and provide for same computational operation on data and parity of the data to determine errors because judicious and repetitive use of the same computational operation function increases efficiency and reduces the cost of developing and maintaining a large program while increasing its quality and reliability (NPL Function, page 1, paragraph 4).
No prior art rejection is given for claims 6, 9-13, 18.
Conclusion
The prior art made of record in Form PTO-892 and not relied upon is considered pertinent to Applicants’ disclosure.
Mazzawi et al. (U.S. Patent Publn. No. 2018/0232477 A1, cited in IDS) teaches hard error simulation and usage thereof. The method comprises obtaining a design of a circuit, which comprises one or more monitoring signals for identifying errors and one or more critical nodes; obtaining a trace of a run of a test of the circuit; and obtaining a hard error fault on a node. The method comprises determining a hard-error test coverage for the hard error fault, wherein the hard-error test coverage is indicative of whether or not the one or more monitoring signals identifies the hard error fault during an execution of the test, and wherein said determining comprises: simulating the execution of the circuit together with the hard error fault and noting whether or not any one or more of the one or more monitoring signals has detected the hard error fault. An indication of the hard-error test coverage may be outputted.
Applicants are required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
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/INDRANIL CHOWDHURY/ Examiner, Art Unit 2114
/ASHISH THOMAS/ Supervisory Patent Examiner, Art Unit 2114