DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/09/24 has been considered by the examiner.
Drawings
The drawings received on 08/30/24 are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 9,753,475 B2).
Lin et al. disclose a feedback type voltage regulator in Figures 1-4.9999
Regarding claim 1. An apparatus (Figure 3) comprising: a first transistor (120) coupled between a power input (VIN) and a power output (Vout), the first transistor being an N-type transistor and having a first transistor control input; a first amplifier stage (201) having a reference input (-), a feedback input (+), and a first amplifier output (V1), the feedback input coupled to the power output; a second amplifier stage (302) having an amplifier input (-) and a second amplifier output, the amplifier input coupled to the first amplifier output, and the second amplifier output coupled to the first transistor control input (120); and a first biasing circuit (t3he current source is a modified multiplier self-biasing circuit with a resistor to generate a current, and then produce a reference voltage through the bias-voltage circuit) coupled to the first transistor control input, the first biasing circuit having an electrical control input coupled to the power output (see col. 4, line 28 to col. 6, line 54).
Allowable Subject Matter
Claims 20-23 are allowed over the cited prior art of record.
Claims 2-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 20 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “a second amplifier stage having an amplifier input and a second amplifier output, the amplifier input coupled to the first amplifier output, and the second amplifier output coupled to the first transistor control input; and a capacitor and a second transistor coupled in series between the first amplifier output and the first transistor control input, the second transistor having a second transistor control input electrically coupled to the power output and the first amplifier output“ in addition to other limitations recited therein.
Dependent claim 21 is allowable by virtue of their dependency.
Claim 22 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “a buffer having a buffer input, a bias input, and a buffer output, the buffer input coupled to the amplifier output; a level shifter having a level shifter input and a level shifter output, the level shifter input coupled to buffer output, and the level shifter output coupled to the transistor control input; a first biasing circuit coupled between the power input and the bias input of the buffer; and a second biasing circuit coupled to the level shifter output and the transistor control input“ in addition to other limitations recited therein.
Dependent claim 23 is allowable by virtue of their dependency.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “wherein the second amplifier stage includes a second transistor, the second transistor having a second transistor control input coupled to the amplifier input and a current input coupled to the second amplifier output“ in addition to other limitations recited therein.
Claim 3 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “a voltage boost circuit coupled to the power input and including a boost voltage output, wherein the first biasing circuit is coupled between the boost voltage output and the first transistor control input“ in addition to other limitations recited therein.
Dependent claims 4 and 5 are allowable by virtue of their dependency.
Claim 6 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “a feedback circuit electrically coupling the power output to the electrical control input of the first biasing circuit“ in addition to other limitations recited therein.
Dependent claims 7-9 are allowable by virtue of their dependency.
Claim 10 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “wherein the first biasing circuit includes a current mirror having a gain ratio greater than one“ in addition to other limitations recited therein.
Claim 11 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “wherein: the second amplifier stage includes a buffer and a level shifter; the buffer includes a buffer input, a buffer output, and a bias input, the buffer input coupled to the first amplifier output; the level shifter includes a level shifter input coupled to the buffer output, and a level shifter output coupled to the second amplifier output; and the apparatus further comprises a second biasing circuit coupled between the power input and the bias input of the buffer“ in addition to other limitations recited therein.
Dependent claims 12-15 are allowable by virtue of their dependency.
Claim 16 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation “a compensation circuit coupled between the first amplifier output and the second amplifier output, the compensation circuit including a capacitive element and a resistive element connected in series between the first amplifier output and the first transistor control input“ in addition to other limitations recited therein.
Dependent claims 17-19 are allowable by virtue of their dependency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhong et al. (US 11,480,985 B2) disclose a low-power voltage regulator with fast transient response.
Li et al. (US 9,146,569 B2) disclose a low drop out regulator and current trimming device.
Examiner has cited particular columns, line numbers and/or paragraphs in the
references applied to the claims above for the convenience of the applicant. Although
the specified citations are representative of the teachings of the art and are applied to
specific limitations within the individual claim(s), other passages and figures may apply
as well.
Additionally, in the event that other prior art is provided and made of record by the
Examiner, as being relevant or pertinent to applicant's disclosure but not relied upon.
The references are provided for the convenience of the applicant.
The Examiner request that the references be considered in any subsequent amendments,
as they are also representative of the art and may apply to the specific limitations of
any newly amended claim(s).
It is respectfully requested from the applicant in preparing amendments or responses, to
fully consider the references in their entirety as potentially teaching all or part of the
claimed invention, as well as the context of the passage as taught by the prior art and/or
disclosed by the Examiner.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADOLF D BERHANE whose telephone number is (571)272-2077. The examiner can normally be reached 7 AM - 10 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ADOLF D BERHANE/Primary Examiner, Art Unit 2838
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