DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chevalier (U.S. Patent 8,804,386).
Claim 1: Chevalier teaches a charge pump (Figure 4) comprising:
a flying capacitor (CFLY);
a push-pull driver (MPo’, MN1’; column 4 lines 40-45, column 6 lines 25-37 where MPo’ and MN1’ are small transistors operated in the second mode of operation, and during the second mode of operation, MPo’ and MN1’ operate in a complementary fashion in the manner described with respect to Figure 2 to push and pull the node CCP) provided on a first end of the flying capacitor (CCP);
a first switch (MN1) provided between the first end of the flying capacitor and a first reference conductor (Gnd);
a second switch (MN3) provided between a second end of the flying capacitor (CCN) and the first reference conductor (Gnd); and
a third switch (MN4) provided between the second end of the flying capacitor and an output terminal (VPUMP),
wherein the push-pull driver comprises a fourth switch (MPo’) and a fifth switch (MN1’), each of the fourth switch and the fifth switch having a first end connected to the first end of the flying capacitor, and
wherein the fourth switch has a second end connected to a second reference conductor (Vdd), the second reference conductor being different from the first reference conductor, and the fifth switch has a second end connected to the first reference conductor (Gnd).
Claim 8: Chevalier further teaches that the first switch (MN1), the second switch (MN3), the third switch (MN4), and the fifth switch (MN1’) are NMOS switches (column 5 lines 11-12), and wherein the fourth switch is a PMOS switch (MPo’; column 5 line 51).
Claim 9: Chevalier further teaches that the first reference conductor is a grounded conductor (Gnd), and wherein the second reference conductor is a power supply line (Vdd).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chevalier in view of Hashimoto (U.S. Patent Application Publication 2005/0104651).
Claim 3: Chevalier teaches the limitations of claim 1 above. Chevalier does not specifically teach first or second current adjusting devices provided on the second end of the fourth and fifth switches.
Hashimoto teaches a charge pump (Figure 1) comprising a push-pull circuit (CS1, CS2, S1 and S2 corresponding to MPo’ and MN1’ of Chevalier) comprising:
a first current adjusting device (CS1) provided on the second end of the fourth switch (between VCC and S1, corresponding to between Vdd and MPo’ of Chevalier); and
a second current adjusting device (CS2) provided on the second end of the fifth switch (between S2 and ground, corresponding to between MN1’ and Gnd of Chevalier),
wherein the first current adjusting device and the second current adjusting device are configured to adjust a current that flows into the flying capacitor ([0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the current adjusting devices taught by Hashimoto in the circuit of Chevalier to inhibit generation of noise at the power supply and the ground ([0034]).
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chevalier.
Claim 10: Chevalier teaches the limitations of claim 1 above. Chevalier further teaches that the first switch (MN1), the second switch (MN3), the third switch (MN4), and the fifth switch (MN1’) are NMOS switches (column 5 lines 11-12), and wherein the fourth switch is a PMOS switch (MPo’; column 5 line 51). Chevalier does not specifically teach that the first switch, the second switch, the third switch and the fifth switch are PMOS switches and the fourth switch is an NMOS switch. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change the transistor types with corresponding logical inputs from NMOS to PMOS and vice versa. Examiner takes Official Notice of the equivalence of an NMOS=PMOS with an inverted input, and PMOS=NMOS with an inverted input for their use in the art and the selection of any of these known equivalents would be within the level of ordinary skill in the art.
Claim 11: Chevalier teaches the limitations of claim 10 above. Chevalier further teaches that the first reference conductor is a grounded conductor (Gnd), and wherein the second reference conductor is a power supply line (Vdd). Chevalier does not specifically teach the first reference conductor is a power supply line, and the second reference conductor is a grounded conductor. However, it would have been obvious to one of ordinary skill in the art to change the power supply line and ground connections while changing the transistor types from NMOS to PMOS and vice versa. Examiner takes Official Notice of the equivalence of these circuit structures to accommodate changing the transistor type for their use in the art and the selection of any of these known equivalents would be within the level of ordinary skill in the art.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chevalier in view of Thiery et al. (U.S. Patent 7,772,919, hereafter Thiery).
Claim 12: Chevalier teaches a charge pump (Figure 4) comprising:
a flying capacitor (CFLY);
a push-pull driver (MPo’, MN1’; column 4 lines 40-45, column 6 lines 25-37 where MPo’ and MN1’ are small transistors operated in the second mode of operation, and during the second mode of operation, MPo’ and MN1’ operate in a complementary fashion in the manner described with respect to Figure 2 to push and pull the node CCP) provided on a first end of the flying capacitor (CCP);
a first switch (MN1) provided between the first end of the flying capacitor and a first reference conductor (Gnd);
a second switch (MN3) provided between a second end of the flying capacitor (CCN) and the first reference conductor (Gnd); and
a third switch (MN4) provided between the second end of the flying capacitor and an output terminal (VPUMP),
wherein the push-pull driver comprises a fourth switch (MPo’) and a fifth switch (MN1’), each of the fourth switch and the fifth switch having a first end connected to the first end of the flying capacitor, and
wherein the fourth switch has a second end connected to a second reference conductor (Vdd), the second reference conductor being different from the first reference conductor, and the fifth switch has a second end connected to the first reference conductor (Gnd).
Chevalier does not specifically teach a plurality of charge pumps, wherein the output terminals of the plurality of charge pumps are connected in common.
Thiery teaches a plurality of charge pumps (10; Figure 2 and Abstract comprising the charge pump circuit of Chevalier), wherein the output terminals of the plurality of charge pumps are connected in common (at VCP; Abstract),
wherein a clock signal for controlling the first to fifth switches (CLK; Figure 5 of Chevalier) included in each of the plurality of charge pumps (for each circuit 10 of Thiery) is input to each of the plurality of charge pumps (via CLK1, CLK2 and CLK3 of Thiery), and
wherein the clock signal has a different phase for each of the plurality of charge pumps (Figure 3A of Thiery).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the plurality of charge pumps taught by Thiery in implementing the charge pumps of Chevalier to provide a charge pump with constant output current and to reduce electrical noise limiting the voltage ripple (column 4 lines 37-41).
Allowable Subject Matter
Claims 2 and 4-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art does not fairly teach or suggest turning the fourth switch and the fifth switch ON or OFF together with the second switch in combination with the limitations of claim 2. Chevalier teaches that the fourth and fifth switches (MPo’ and MN1’) are small sized and operated in a different mode than the large sized transistors (column 6 lines 29-37).
Regarding claims 4 and 5, the prior art does not fairly teach or suggest an error amplifier in combination with the limitations of claims 4 and 5.
Regarding claim 6, the prior art does fairly teach or suggest a second clock path connected to the clock path via a first voltage-shifting capacitor; and a second inverted clock connected to the inverted clock path via a second voltage-shifting capacitor, wherein an offset clock signal and inverted clock signal having a dc component that is offset with respect to the clock signal and inverted clock signal in combination with the limitations of claim 6. Claim 7 is objected to merely for being dependent on claim 6.
Claims 13-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 13, the prior art does not fairly teach or suggest turning the fourth switch and the fifth switch ON or OFF together with the second switch in combination with the limitations of claim 13. Chevalier teaches that the fourth and fifth switches (MPo’ and MN1’) are small sized and operated in a different mode than the large sized transistors (column 6 lines 29-37). Claims 14-20 are allowed merely for being dependent on claim 13.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
U.S. Patent Application Publication 2008/0122505
U.S. Patent 10,886,834
U.S. Patent 12,015,339
U.S. Patent 12,401,213
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLLEEN J O'TOOLE whose telephone number is (571)270-1273. The examiner can normally be reached Monday - Friday, 9:00 am - 6:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.J.O/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849