DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in respond to Applicant’s amendment filed on May 18, 2026, claims 1-20 are pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 7-9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (US 2022/0238167 A1, hereinafter Suzuki) in view of Han et al. (US 2021/0050066 A1, hereinafter Han).
Regarding claim 1, Suzuki discloses a semiconductor memory device (figure 2, 1) comprising: a memory cell array (figure 2, 10); a control circuit (figure 2, 12) configured to perform a first operation to access the memory cell array and then a second operation to access the memory cell array ([0046], logic control circuit 12 receives the signals from the memory controller 2, and controls the input/output circuit 11 based on the received signals); and a voltage generation circuit (figure 2, 15) configured to generate a first operation voltage, which is supplied to from an output terminal of the voltage generation circuit to the memory cell array during the first operation, and a second operation voltage, which is supplied from the output terminal to the memory cell array during the second operation ([0049], the voltage generation circuit 15 generates a voltage used for the erase operation, the write operation, and the read operation based on an instruction from the sequencer 14, and supplies the generated voltage to the row decoder 16, the sense amplifier module 17, and the source line driver 18). Suzuki differs from the claimed invention in not specifically teaching that the control circuit is configured to perform the first operation using the first operation voltage, perform the second operation using the second operation voltage, and control the voltage generation circuit to maintain a voltage output from the output terminal the voltage generation circuit to be at the first operation voltage after the first operation until the second operation voltage starts to be supplied to the memory cell array for the second operation. Han teaches that the control circuit is configured to perform the first operation using the first operation voltage (figure 7, S730 and [0091], a control logic 300 controlling the peripheral circuit 200 to perform an erase voltage application operation), perform the second operation using the second operation voltage ([0104], the control logic 300 sets a currently set erase voltage (also referred to as the last set erase voltage), and control the voltage generation circuit to maintain a voltage output from the output terminal the voltage generation circuit to be at the first operation voltage after the first operation until the second operation voltage starts to be supplied to the memory cell array for the second operation (figure 7, S770 and [0097]-[0099], when it is determined that the first erase verify operation has passed, a second erase verify operation is performed) in order to improve a threshold voltage distribution of memory cells in an operating system of the memory device ([0007]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Suzuki in having that the control circuit is configured to perform the first operation using the first operation voltage, perform the second operation using the second operation voltage, and control the voltage generation circuit to maintain a voltage output from the output terminal the voltage generation circuit to be at the first operation voltage after the first operation until the second operation voltage starts to be supplied to the memory cell array for the second operation, as per teaching of Han, in order to improve a threshold voltage distribution of memory cells in an operating system of the memory device.
Regarding claim 2, Suzuki teaches that the first operation is one of a write operation, a read operation, and an erase operation, and the second operation is the same one of the write operation, the read operation, and the erase operation ([0049], the voltage generation circuit 15 generates a voltage used for the erase operation, the write operation, and the read operation).
Regarding claim 7, Suzuki does not teach the claimed limitations. However, Han teaches that the memory cell array includes a first memory cell, a second memory cell, a first source line connected to the first memory cell ([0093], row decoder 220 controls the word lines WL1 to WLn of the selected memory block MB1 to be in a floating state and applies a select line voltage to each of the drain select line DSL and the source select line SSL), and a second source line connected to the second memory cell ([0099], the row decoder 220 applies the second erase verify voltage Vverify2 to a selected word line of the selected memory block MB1), the first operation is an erase operation with respect to the first memory cell, and the first operation voltage is supplied from the output terminal to the first source line during the first operation ([0094], the erase operation may be applied to an erase operation for erasing data stored in memory cells, using an FN tunneling scheme, by applying an erase voltage having a high-potential level to the source line), and the second operation is a read operation with respect to the second memory cell, and the second operation voltage is supplied from the output terminal to the second source line during the second operation ([0047]-[0048] and [0107], memory controller 1200 may control a data access operation of the memory device 1100, e.g., a program operation, an erase operation, a read operation, or the like under the control of a processor 3100, such that the source line driver 270 may electrically couple the source line SL and a ground node in a program, read, or verify operation). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Suzuki in having that the memory cell array includes a first memory cell, a second memory cell, a first source line connected to the first memory cell, and a second source line connected to the second memory cell, the first operation is an erase operation with respect to the first memory cell, and the control circuit is configured to supply the first operation voltage is supplied from the output terminal generated by the voltage generation circuit to the first source line during the first operation, and the second operation is a read operation with respect to the second memory cell, and the control circuit is configured to supply the second operation voltage is supplied from the output terminal generated by the voltage generation circuit to the second source line during the second operation, as per teaching of Han, in order to improve a threshold voltage distribution of memory cells in an operating system of the memory device.
Regarding claim 8, Suzuki does not teach the claimed limitations, but Han teaches that the first operation voltage is an erase voltage, and the second operation voltage is equal to the first operation voltage ([0104], the control logic 300 sets a currently set erase voltage, i.e., also referred to as the last set erase voltage, as a start erase voltage). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Suzuki in having that the first operation voltage is an erase voltage, and the second operation voltage is equal to the first operation voltage, as per teaching of Han, in order to improve a threshold voltage distribution of memory cells in an operating system of the memory device.
Regarding claim 9, the limitations of the claim are rejected as the same reasons as set forth in claim 2.
Regarding claim 18, Suzuki discloses a memory system as shown in figure 1 comprising: the semiconductor memory device (figure 1, 3); and a memory controller (figure 1, 2) connectable to a host (figure 1, 4) and configured to control the semiconductor memory device in accordance with a command from the host ([0032], the memory controller 2 receives a command from the host device 4 and controls the semiconductor storage device 1 based on the received command).
Claims 3-4 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (US 2022/0238167 A1, hereinafter Suzuki) in view of Han et al. (US 2021/0050066 A1 hereinafter Han) as applied to claims above, and further in view of Fujiu (US 2009/0147595 A1).
Regarding claims 3-4, the combination of Suzuki and Han discloses that the memory cell array includes a first memory cell and a word line connected to the first memory cell, the first operation is a write operation with respect to the first memory cell, and the first operation voltage is supplied from the output terminal to the word line during the first operation (Han [0095], the voltage generating circuit 210 generates a first erase verify voltage Vverify1, and the row decoder 220 applies the first erase verify voltage Vverify1 to the word lines WL1 to WLn of the selected memory block MB1 in the first erase verify operation), wherein the first operation voltage is a first program voltage and the second operation voltage is a second program voltage different from the first program voltage (Han [0050], erase voltage setting operation may include an erase voltage application operation for applying an initially set erase voltage, a first erase verify operation using a first erase verify voltage, a second erase verify operation using a second erase verify voltage lower than the first erase verify voltage). The combination of Suzuki and Han differs from the claimed invention in not specifically teaching that the second operation is a write operation with respect to the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation. However, Fujiu teaches switching element control signal SWprg is turned to "H" (S2), and the boosting circuit 11 generates an output voltage Vprg boosted up to the level of writing voltage Vprg1 when the writing sequence is started, wherein a first voltage necessary for writing data into the memory cell MC ([0040]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Suzuki and Han in having that the second operation is a write operation with respect to the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation, as per teaching of Fujiu, in order to save current consumption.
Regarding claims 10-11, the combination of Suzuki and Han discloses that the memory cell array includes a first memory cell (Han [0040], memory cell array 100 may include a plurality of memory blocks MB1 to MBk), a word line connected to the first memory cell ([0040], local lines LL and bit lines BL1 to BLn may be coupled to the memory blocks MB1 to MBk 110), and a source line connected to the first memory cell ([0040], the local lines LL may include word lines, drain and source select lines, and source lines SL), the first operation is an erase operation with respect to the first memory cell, and the first operation voltage is supplied from the output terminal to the source line during the first operation ([0095], the voltage generating circuit 210 generates a first erase verify voltage Vverify1, and the row decoder 220 applies the first erase verify voltage Vverify1 to the word lines WL1 to WLn of the selected memory block MB1 in the first erase verify operation). The combination of Suzuki and Han differs from the claimed invention in not specifically teaching that the second operation is a write operation with respect to the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation. Fujiu teaches switching element control signal SWprg is turned to "H" (S2), and the boosting circuit 11 generates an output voltage Vprg boosted up to the level of writing voltage Vprg1 when the writing sequence is started, wherein a first voltage necessary for writing data into the memory cell MC ([0040]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Han in having that the second operation is a write operation with respect to the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation, as per teaching of Fujiu, in order to save current consumption.
Regarding claim 11, the combination of Suzuki and Han discloses that the memory cell array includes a first memory cell and a word line connected to the first memory cell, the first operation is an erase operation with respect to the first memory cell, and the first operation voltage is supplied from the output terminal to the source line during the first operation (Han [0095], the voltage generating circuit 210 generates a first erase verify voltage Vverify1, and the row decoder 220 applies the first erase verify voltage Vverify1 to the word lines WL1 to WLn of the selected memory block MB1 in the first erase verify operation). The combination of Suzuki and Han differs from the claimed invention in not specifically teaching that the second operation is a write operation with respect to a memory cell other than the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation. However, Fujiu teaches switching element control signal SWprg is turned to "H" (S2), and the boosting circuit 11 generates an output voltage Vprg boosted up to the level of writing voltage Vprg1 when the writing sequence is started, wherein a first voltage necessary for writing data into the memory cell MC ([0040]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Suzuki and Han in having that the second operation is a write operation with respect to a memory cell other than the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation, as per teaching of Fujiu, in order to save current consumption.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (US 2022/0238167 A1, hereinafter Suzuki) in view of Han et al. (US 2021/0050066 A1 hereinafter Han) as applied to claims above, and further in view of Ho et al. (US 2011/0085378 A1, hereinafter Ho).
Regarding claim 5, the combination of Suzuki and Han teaches that the memory cell array includes a first memory cell and a word line connected to the first memory cell, the first operation is a read operation with respect to a memory cell other than the first memory cell, and the first operation voltage is supplied from the output terminal to the word line during the first operation (Han [0047], the pass/fail check circuit 260 may generate a reference current in response to an allow bit VRY_BIT<#>, and output a pass signal PASS in a read operation and a verify operation). The combination of Suzuki and Han differs from the claimed invention in not specifically teaching that the second operation is a read operation with respect to a memory cell other than the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation. However, Ho teaches that the memory cells are read by applying a reference voltage in a first reading operation and the memory cells are read by applying the moved reference voltage in a second read operation such that other pages are read applying the initial word line reference voltage after learning ([0051]-[0052]) in order to improve read speed. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Suzuki and Han in having that the second operation is a read operation with respect to a memory cell other than the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation, as per teaching of Ho, in order to improve read speed.
Regarding claim 6, Ho teaches that the first operation voltage is a read pass voltage, and the second operation voltage is equal to the first operation voltage ([0051], respective initial word line reference voltage for other pages is set as the target word line reference voltage for the initial page P(0) such that the second operation voltage is equal to the first operation voltage, i.e., word line reference voltage) in order to improve read speed.
Allowable Subject Matter
Claims 12-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach nor suggested “a control circuit configured to perform a first operation to access the memory cell array, a second operation to access the memory cell array after the first operation, and a third operation to access the memory cell array after the second operation; and a voltage generation circuit configured to generate a first operation voltage, which is supplied to from an output terminal of the voltage generation circuit to the memory cell array during the first operation, a second operation voltage, which is supplied from the output terminal to the memory cell array during the second operation, and a third operation voltage, which is supplied to from the output terminal of the voltage generation circuit to the memory cell array during the third operation … and the control circuit is configured to control the voltage generation circuit to maintain the voltage output from the output terminal to be at the second operation voltage after the second operation until the third operation voltage starts to be supplied to the memory cell array for the third operation” as recited in amended claim 12; and “the semiconductor memory device is configured to operate in a first mode and a second mode, in the first mode, the control circuit is configured to control the voltage generation circuit to maintain the voltage output from the output terminal to be at the first operation voltage after the first operation until the second operation voltage starts to be supplied to the memory cell array for the second operation, and in the second mode, the control circuit is configured to control the voltage generation circuit to cause the voltage output from the output terminal to drop from the first operation voltage after the first operation and before the second operation voltage starts to be supplied to the memory cell array for the second operation” as recited in claim 14.
Claims 13 and 15-17 are allowed because of depending on the allowable claims 12 and 14, respectively.
Claims 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach nor suggest “wherein the control circuit is configured to perform the first operation in response to a first command input from outside of the semiconductor memory device, and the control circuit is configured to control the voltage generation circuit to maintain the voltage generated by the voltage generation circuit to be at the first operation voltage based on a second command input from the outside of the semiconductor memory device”.
Claim 20 is objected because of depending of claim 19, containing the same allowable subject matter.
Response to Arguments
Applicant’s arguments with respect to claims 1-11 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kurosawa et al. (US 2026/0080951 A1) discloses a semiconductor memory device operating threshold voltages of the control electrodes of the high-side transistor and the low-side transistor to values higher than the target values due to the substrate bias effect, so that current consumption can be reduced (abstract and figure 2).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHUO H LI whose telephone number is (571)272-4183. The examiner can normally be reached Mon. Tue. and Thurs. 8:00-4:00 PM.
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/ZHUO H LI/Primary Examiner, Art Unit 2133
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