DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement filed on August 30, 2024 is considered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7-9 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han et al. (US 2021/0050066 A1 hereinafter Han).
Regarding claim 1, Han discloses a semiconductor memory device (figure 2, 1100) comprising: a memory cell array (figure 2, 100); a control circuit (figure 2, 300) configured to perform a first operation to access the memory cell array and then a second operation to access the memory cell array ([0050], control logic 300 may control the peripheral circuit 200 to perform an erase voltage setting operation for optimizing and setting an erase voltage used in an erase operation of the memory device, including an erase voltage application operation for applying an initially set erase voltage, a first erase verify operation using a first erase verify voltage, a second erase verify operation using a second erase verify voltage); and a voltage generation circuit (figure 2, 210) configured to generate a first operation voltage, which is supplied to from an output terminal of the voltage generation circuit to the memory cell array during the first operation, and a second operation voltage, which is supplied from the output terminal to the memory cell array during the second operation ([0042], voltage generating circuit 210 may generate various operating voltages Vop used for program, read, and erase operations in response to an operation signal OP_CMD), wherein the control circuit is configured to control the voltage generation circuit to maintain a voltage output from the output terminal to be at the first operation voltage after the first operation until the second operation voltage starts to be supplied to the memory cell array for the second operation ([0102]-[0104], the control logic 300 again performs the above-described operations from the second erase verify operation subsequently, and the control logic 300 sets a currently set erase voltage (also referred to as the last set erase voltage) as a start erase voltage of the erase operation when it is determined the control logic 300 sets a currently set erase voltage (also referred to as the last set erase voltage) as a start erase voltage of the erase operation).
Regarding claim 2, Han discloses that the first operation is one of a write operation, a read operation, and an erase operation, and the second operation is the same one of the write operation, the read operation, and the erase operation ([0080], an algorithm for performing various overall operations, e.g., a program operation, a read operation, an erase operation, and the like, on the memory device may be stored in the ROM).
Regarding claim 7, Han discloses that the memory cell array includes a first memory cell, a second memory cell, a first source line connected to the first memory cell ([0093], row decoder 220 controls the word lines WL1 to WLn of the selected memory block MB1 to be in a floating state and applies a select line voltage to each of the drain select line DSL and the source select line SSL), and a second source line connected to the second memory cell ([0099], the row decoder 220 applies the second erase verify voltage Vverify2 to a selected word line of the selected memory block MB1), the first operation is an erase operation with respect to the first memory cell, and the first operation voltage is supplied from the output terminal to the first source line during the first operation ([0094], the erase operation may be applied to an erase operation for erasing data stored in memory cells, using an FN tunneling scheme, by applying an erase voltage having a high-potential level to the source line), and the second operation is a read operation with respect to the second memory cell, and the second operation voltage is supplied from the output terminal to the second source line during the second operation ([0047]-[0048] and [0107], memory controller 1200 may control a data access operation of the memory device 1100, e.g., a program operation, an erase operation, a read operation, or the like under the control of a processor 3100, such that the source line driver 270 may electrically couple the source line SL and a ground node in a program, read, or verify operation).
Regarding claim 8, Han teaches that the first operation voltage is an erase voltage, and the second operation voltage is equal to the first operation voltage ([0104], the control logic 300 sets a currently set erase voltage, i.e., also referred to as the last set erase voltage, as a start erase voltage).
Regarding claim 9, the limitations of the claim are rejected as the same reasons as set forth in claim 2.
Regarding claim 18, Han discloses a memory system (figure 1) comprising: the semiconductor memory device according to claim 1 (figure 1, 1100); and a memory controller (figure 1, 1200) connectable to a host (figure 1, 2000) and configured to control the semiconductor memory device in accordance with a command from the host ([0034], the memory system 1000 may include a memory device 1100 for storing data and a memory controller 1200 for controlling the memory device 1100 under the control of a host 2000).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3-4 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2021/0050066 A1 hereinafter Han) in view of Fujiu (US 2009/0147595 A1).
Regarding claim 3, Han discloses that the memory cell array includes a first memory cell and a word line connected to the first memory cell, the first operation is a write operation with respect to the first memory cell, and the first operation voltage is supplied from the output terminal to the word line during the first operation ([0095], the voltage generating circuit 210 generates a first erase verify voltage Vverify1, and the row decoder 220 applies the first erase verify voltage Vverify1 to the word lines WL1 to WLn of the selected memory block MB1 in the first erase verify operation). Han differs from the claimed invention in not specifically teaching that the second operation is a write operation with respect to the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation. However, Fujiu teaches switching element control signal SWprg is turned to "H" (S2), and the boosting circuit 11 generates an output voltage Vprg boosted up to the level of writing voltage Vprg1 when the writing sequence is started, wherein a first voltage necessary for writing data into the memory cell MC ([0040]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Han in having that the second operation is a write operation with respect to the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation, as per teaching of Fujiu, in order to save current consumption.
Regarding claim 4, Han discloses that the first operation voltage is a first program voltage and the second operation voltage is a second program voltage different from the first program voltage ([0050], erase voltage setting operation may include an erase voltage application operation for applying an initially set erase voltage, a first erase verify operation using a first erase verify voltage, a second erase verify operation using a second erase verify voltage lower than the first erase verify voltage).
Regarding claim 10, Han discloses that the memory cell array includes a first memory cell ([0040], memory cell array 100 may include a plurality of memory blocks MB1 to MBk), a word line connected to the first memory cell ([0040], local lines LL and bit lines BL1 to BLn may be coupled to the memory blocks MB1 to MBk 110), and a source line connected to the first memory cell ([0040], the local lines LL may include word lines, drain and source select lines, and source lines SL), the first operation is an erase operation with respect to the first memory cell, and the first operation voltage is supplied from the output terminal to the source line during the first operation ([0095], the voltage generating circuit 210 generates a first erase verify voltage Vverify1, and the row decoder 220 applies the first erase verify voltage Vverify1 to the word lines WL1 to WLn of the selected memory block MB1 in the first erase verify operation). Han differs from the claimed invention in not specifically teaching that the second operation is a write operation with respect to the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation. Fujiu teaches switching element control signal SWprg is turned to "H" (S2), and the boosting circuit 11 generates an output voltage Vprg boosted up to the level of writing voltage Vprg1 when the writing sequence is started, wherein a first voltage necessary for writing data into the memory cell MC ([0040]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Han in having that the second operation is a write operation with respect to the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation, as per teaching of Fujiu, in order to save current consumption.
Regarding claim 11, Han discloses that the memory cell array includes a first memory cell and a word line connected to the first memory cell, the first operation is an erase operation with respect to the first memory cell, and the first operation voltage is supplied from the output terminal to the source line during the first operation ([0095], the voltage generating circuit 210 generates a first erase verify voltage Vverify1, and the row decoder 220 applies the first erase verify voltage Vverify1 to the word lines WL1 to WLn of the selected memory block MB1 in the first erase verify operation). Han differs from the claimed invention in not specifically teaching that the second operation is a write operation with respect to a memory cell other than the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation. However, Fujiu teaches switching element control signal SWprg is turned to "H" (S2), and the boosting circuit 11 generates an output voltage Vprg boosted up to the level of writing voltage Vprg1 when the writing sequence is started, wherein a first voltage necessary for writing data into the memory cell MC ([0040]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Han in having that the second operation is a write operation with respect to a memory cell other than the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation, as per teaching of Fujiu, in order to save current consumption.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2021/0050066 A1 hereinafter Han) in view of Ho et al. (US 2011/0085378 A1, hereinafter Ho)
Regarding claim 5, Han teaches that the memory cell array includes a first memory cell and a word line connected to the first memory cell, the first operation is a read operation with respect to a memory cell other than the first memory cell, and the first operation voltage is supplied from the output terminal to the word line during the first operation ([0047], the pass/fail check circuit 260 may generate a reference current in response to an allow bit VRY_BIT<#>, and output a pass signal PASS in a read operation and a verify operation). Han differs from the claimed invention in not specifically teaching that the second operation is a read operation with respect to a memory cell other than the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation. However, Ho teaches that the memory cells are read by applying a reference voltage in a first reading operation and the memory cells are read by applying the moved reference voltage in a second read operation such that other pages are read applying the initial word line reference voltage after learning ([0051]-[0052]) in order to improve read speed. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Han in having that the second operation is a read operation with respect to a memory cell other than the first memory cell, and the second operation voltage is supplied from the output terminal to the word line during the second operation, as per teaching of Ho, in order to improve read speed.
Regarding claim 6, Ho teaches that the first operation voltage is a read pass voltage, and the second operation voltage is equal to the first operation voltage ([0051], respective initial word line reference voltage for other pages is set as the target word line reference voltage for the initial page P(0) such that the second operation voltage is equal to the first operation voltage, i.e., word line reference voltage) in order to improve read speed.
Allowable Subject Matter
Claims 12-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach nor suggest “wherein the control circuit is configured to perform a third operation to access the memory cell array after the second operation, the voltage generation circuit is configured to generate a third operation voltage, which is supplied to from the output terminal of the voltage generation circuit to the memory cell array during the third, and the control circuit is configured to control the voltage generation circuit to maintain the voltage output from the output terminal to be at the second operation voltage after the second operation until the third operation voltage starts to be supplied to the memory cell array for the third operation” as recited in claim 12; and “wherein the semiconductor memory device is configured to operate in a first mode and a second mode, in the first mode, the control circuit is configured to control the voltage generation circuit to maintain the voltage output from the output terminal to be at the first operation voltage after the first operation until the second operation voltage starts to be supplied to the memory cell array for the second operation, and in the second mode, the control circuit is configured to control the voltage generation circuit to cause the voltage output from the output terminal to drop from the first operation voltage after the first operation and before the second operation voltage starts to be supplied to the memory cell array for the second operation” as recited in claim 14.
Claims 13 and 15-17 are also objected because of depending on claims 12 and 14, respectively, containing the same allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hwang et al. (US 2022/0121520 A1) discloses a memory system includes: a plurality of storage regions, each including a plurality of memory cells; and a controller configured to provide a plurality of read retry sets, determine an applying order of the plurality of read retry sets based on characteristics of a read error occurred in a first storage region among the plurality of storage regions, and apply at least one of the read retry sets, based on the applying order, for a read retry operation performed on the first storage region (abstract).
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/ZHUO H LI/ Primary Examiner, Art Unit 2133