DETAILED ACTION
Status of the Claims
The filing dated 8/30/24 is entered. Claims 1-19 are pending.
Foreign Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 16-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen, US-20190244974.
In regards to claim 1, Chen discloses a display substrate (Par. 0002 display panel and apparatus, which has a housing, i.e. substrate), comprising: a base substrate (Fig. 1-4, substrate with surface S1 and S2) including a bonding area (Fig. 1-4, 20 bonding region); and first connecting pins (Fig. 1-4, 21 pins) and second connecting pins (Fig. 1-4, 22 pins) in the bonding area, wherein: along a direction from the first connecting pins to the second connecting pins, an insulating structure is provided between the first connecting pins and the second connecting pins (Fig. 1-4, insulation between pins 21 and 22); and one first connecting pin and one second connecting pin adjacent to each other are disposed in different conductive layers.
In regards to claim 18, Chen discloses touch display panel (Par. 0002 display panel and apparatus; touch is only mentioned in preamble and has no bearing on the rest of the claim and such is not given patentable weight), comprising a display substrate (Par. 0002 display panel and apparatus, which has a housing, i.e. substrate), wherein the display substrate includes: a base substrate (Fig. 1-4, substrate with surface S1 and S2) including a bonding area (Fig. 1-4, 20 bonding region); and first connecting pins (Fig. 1-4, 21 pins) and second connecting pins (Fig. 1-4, 22 pins) in the bonding area, wherein: along a direction from the first connecting pins to the second connecting pins, an insulating structure is provided between the first connecting pins and the second connecting pins (Fig. 1-4, insulation between pins 21 and 22); and one first connecting pin and one second connecting pin adjacent to each other are disposed in different conductive layers (Fig. 1-4, pins 21 and 22 on different layers).
In regards to claim 19, Chen discloses a touch display device comprising a touch display panel (Par. 0002 display panel and apparatus; touch is only mentioned in preamble and has no bearing on the rest of the claim and such is not given patentable weight), wherein: the touch display panel includes a display substrate (Par. 0002 display panel and apparatus, which has a housing, i.e. substrate); and the display substrate includes: a base substrate (Fig. 1-4, substrate with surface S1 and S2) including a bonding area (Fig. 1-4, 20 bonding region); and first connecting pins (Fig. 1-4, 21 pins) and second connecting pins (Fig. 1-4, 22 pins) in the bonding area, wherein: along a direction from the first connecting pins to the second connecting pins, an insulating structure is provided between the first connecting pins and the second connecting pins (Fig. 1-4, insulation between pins 21 and 22); and one first connecting pin and one second connecting pin adjacent to each other are disposed in different conductive layers (Fig. 1-4, pins 21 and 22 on different layers).
In regards to claim 16, Chen discloses the first connection pins are connected to a power line, a clock signal line, a data line, an idle line or a touch line; and the second connection pins are connected to a power line, a clock signal line, a data line, an idle line or a touch line (Par. 0045 “first transmission lines 31 and the second transmission lines 32 may be used to transmit display signals. The display signals may include at least one of data signals, high-level power source signals, low-level power source signals, reference potential signals, clock signals, constant high-level signals, constant low-level signals, and initial scanning signals, etc.”).
In regards to claim 17, Chen discloses the first connecting pins and the second connecting pins are used to bond to a flexible circuit board and/or a driving chip (Par. 0006 “display panel includes a display region and a bonding region bonding a flexible circuit board with the display panel”).
Allowable Subject Matter
Claims 2-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 2, the prior art of record fails to disclose, teach or fairly suggest to one of ordinary skill in the art, in conjunction with all the other claimed limitations: a display substrate and specifically including “a first conductive layer located on one side of the base substrate, wherein the first connecting pins are located in the first conductive layer in the bonding area; a first insulating layer located on the first conductive layer, wherein the first insulating layer includes a plurality of first hollow areas and each of the plurality of first hollow area exposes at least a portion of one corresponding first connecting pin; a second conductive layer located on the first insulating layer, wherein: the second connecting pins are located in the second conductive layer, and the first connecting pins and the second connecting pins are alternately arranged along the direction from the first connecting pins to the second connecting pins; and a second insulating layer located on the second conductive layer, wherein: the second insulating layer includes second hollow areas and third hollow areas; each second hollow area exposes at least a portion of one corresponding first hollow area and each third hollow area exposes at least a portion of one corresponding second connecting pin.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY A ALMEIDA whose telephone number is (571)270-3143. The examiner can normally be reached M-Th 9AM-730PM.
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/CORY A ALMEIDA/Primary Examiner, Art Unit 2628 9/18/26
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