DETAILED ACTION
Re Application No. 18/821821, this action responds to the amended claims dated 10/27/2025.
At this point, claims 1-20 have been amended, and are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Examiner acknowledges Applicant’s amended claims dated 10/27/2025. In view of the amendment, Examiner’s prior rejections under 35 USC § 112(b) have been rendered moot, and are accordingly withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hasfar et al (US 8917471 B1) [hereinafter Hasfer 1], which incorporates by reference Hasfar et al (US 2015/0120995) [hereinafter Hasfer 2].
Re claim 1, Hasfar 1 discloses the following:
A control method, comprising: obtaining a trigger signal that changes an operation status of an electronic device; and controlling a target storage member of the electronic device to switch to an application mode corresponding to the trigger signal, the application mode comprising a first application mode or a second application mode (col. 5, lines 22-55). The DSD (storage member/electronic device) may enter or exit a high-speed suppression (HSS) mode (first application mode or second application mode) in response to receiving an indication from a host, or detecting activity of the host (in response to a trigger signal);
the target storage member comprising a first data interface, a second data interface, a controller core, and a storage area (Fig. 2). The storage device (target storage member) contains an interface between solid state memory/non-volatile cache (first data interface), a read/write channel (second data interface), a controller (controller core), and the solid state memory/non-volatile cache/disk pack (collectively “a storage area”);
wherein, when the target storage member is in the first application mode, the target storage member responds to first data read/write operations through a first data read/write path formed by the first data interface, the controller core, and the storage area (Fig. 2, solid state memory 128, read/write channel 124, disk 134; col. 4, lines 13-44). In HSS mode, the system can perform deferred writes and reads using the solid state memory to avoid having to spin up the hard drive; accordingly, the target storage member can respond to the read/write operations over a first data path formed by the controller, the solid state disk, and the interface between them (first data interface);
wherein, when the target storage member is in the second application mode, the target storage member responds to second data read/write operations through a second data read/write path formed by the second data interface, the controller core, and the storage area, and the first data read/write path and the second data read/write path are different from one another (Fig. 2, solid state memory 128, read/write channel 124, disk 134; col. 4, lines 45-62). Hasfar discloses a DSD (electronic devices) which contains a path to the solid state memory, as well as another path to the disk (i.e. read/write channel 124) (second data read/write path), which is used when the system exits HSS mode (Fig. 2). Additionally, even if the device is in HSS mode, wherein spin-ups of the disk are minimized and SSD/cache accesses are prioritized, a device may still access the disk over the read/write channel 124 if the spindle is already spun up (col. 4, lines 45-62). Either the non-HSS mode, or the HSS mode in which the disk is already spun up, can be considered a “second application mode” utilizing a second read/write path to data;
the target storage member is associated with first configuration parameters when the target storage member is in the first application mode, the target storage member is associated with second configuration parameters when the target storage member is in the second application mode, and the first configuration parameters are different from the second configuration parameters (Figs. 4-5). The way that storage services operations (configuration parameters) are different based on whether or not the system is in HSS mode (i.e. they are different in different modes).
Hasfar 1 discloses the limitations of claim 1; however, it discloses them as various examples, and it is unclear whether each element appears in a single embodiment and, indeed, may appear over multiple disclosures (i.e. Hasfar 1 and 2); nevertheless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine these examples into a single embodiment, because it would be obvious to make the examples integral (MPEP § 2144.04(V)(B)); furthermore, Hasfar 1 discloses incorporating Hasfar 2 by reference (col. 4, lines 40-44)
Re claim 2, Hasfar 1 discloses the method of claim 1, and further discloses the following:
wherein controlling the target storage member of the electronic device to switch to the application mode corresponding to the trigger signal includes: in response to the trigger signal comprising a first trigger signal for the electronic device to switch from a first operation status to a second operation status, loading a boot system of the electronic device from the target storage member in the first application mode (col. 4, lines 26-44). Furthermore, this limitation is a conditional limitation in a method claim, and as such, the broadest reasonable interpretation is that this contingent limitation is not performed, as the condition will not necessarily occur (MPEP § 2111.04(II); see also Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016)). Nevertheless, in the interest of furthering compact prosecution, Examiner interprets it to mean receiving a signal to switch the system to a boot mode, and loading a boot system from memory for this mode. Hasfar 1 discloses detecting a power up (trigger signal), which places the device into a spin-less drive boot (first application mode/first or second application status), and loads information necessary for booting (boot system) from the memory;
after the boot system completes a target task, controlling the target storage member to switch from the first application mode to the second application mode to allow the target storage member to respond to a data read/write operation of a member of the electronic device (Hasfar 2, Fig. 3; ¶ 23, 30, and 32; claim 4). It is noted that the limitation “after the boot system completes a target task” is conditional, and is thus not required under MPEP § 2111.04(II) (see § i. above). Nonetheless, in the interest of furthering compact prosecution, Hasfar 2 discloses that the method has a spin-less boot mode (first application mode/operation status), and after booting is complete, the DSD (target storage member) switches from boot mode to normal mode, wherein in normal mode the hard disks can be accessed;
wherein power consumption of the target storage member in the first application mode is lower than power consumption of the target storage member in the second application mode (col. 4, lines 6-44). When the system is operating in high spindle suppression/spin-less drive boot modes (first application mode), it uses less power due to the spindle staying powered down, versus a normal mode (second application mode).
Re claim 3, Hasfar 1 discloses the method of claim 1, and further discloses the following:
controlling the target storage member of the electronic device to switch to the application mode corresponding to the trigger signal includes at least one of: in response to the trigger signal comprising a second trigger signal of the electronic device switching from a second operation status to a first operation status, controlling the target storage member to switch from the second application mode to the first application mode; in response to the trigger signal comprising a third trigger signal of the electronic device switching from a third operation status to the first operation status, controlling the target storage member to switch from the second application mode to the first application mode; or in response to the trigger signal comprising a fourth trigger signal of the electronic device switching from the second or third operation status to a fourth operation status, controlling the target storage member to switch from the second application mode to the third application mode (col. 5, lines 12-44). This limitation is subject to interpretation under MPEP § 2111.04(II) (see claim 2 above). Accordingly, each of the 3 conditions may or may not actually occur; accordingly, the language “at least one of” does not clearly require at least one of them to actually occur, but rather, at least one of them may potentially occur. Hasfar discloses entering HSS mode from normal mode, or exiting HSS back to normal mode (switching between modes/statuses), based on an indication (trigger signal) from the host;
wherein the power consumption of the target storage member in the second application mode is greater than the power consumption mode of the target storage member in the first application mode (col. 4, lines 6-44). Since the HSS mode (first application mode) uses less power than normal mode (second application mode), conversely, normal mode uses more power than HSS mode.
Re claim 4, Hasfar 1 discloses the method of claim 3, and further discloses that controlling the target storage member of the electronic storage device to switch the application mode corresponding to the trigger signal includes: controlling the target storage member to switch to a corresponding data interface and/or a power parameter to respond to first or second data read/write operations from the electronic device (col. 4, lines 13-62). The application mode can be set to a HSS/spin-less boot mode or a normal mode, which determines whether data accesses the cache/SSD, or the hard disk via the read/write data interface. It also utilizes power management (power parameter) to minimize hard drive spin-up in response to read/write operations.
Re claim 5, Hasfar 1 discloses the method of claim 4, and further discloses the following:
controlling the target storage member to switch from the first application mode to the second application mode includes: controlling the target storage member to switch from the first data interface to the second data interface, and controlling the target storage member to switch from a first power parameter to a second power parameter, to respond to the second data read/write operations of a member of the electronic device through the second data interface; and/or controlling the target storage member to switch from the second application mode to the first application mode includes: controlling the target storage member to switch from the second data interface to the first data interface, and controlling the target storage member to switch from the second power parameter to the first power parameter, to respond to the first data read/write operations from the electronic device through the first data interface (Fig. 2; col. 3, line 66 to col. 4, line 62). In the HSS/spin-less drive boot mode (first application mode), the system avoids hard drive spin-ups and services requests from the cache/SSD, or, if necessary, from the hard drive via the cache/SSD, if the hard drive is spun up (via the first data interface), saving power (first power parameter). In normal mode, data is serviced from the hard drive (second data interface). Furthermore, it is unclear whether the limitation “to respond to the [first/second] data read/write operations” is a condition for controlling the target storage member to switch modes, in which case it would be interpreted under MPEP § 2111.04(II);
wherein a data read/write rate of the target storage member performed through the first data interface is less than a data read/write rate of the target storage member performed through the second data interface, and power consumption of the target storage member in the first power parameter is less than power consumption of the target storage member in the second power parameter (col. 4, lines 45-62). In HSS mode (first mode), the power consumption is reduced by avoiding hard drive spin-ups. Additionally, in the case of a read miss, (a data read/write rate), if the hard drive is not already spun up, it must wait until it is spun up; alternatively, even if it is spun up, it is serviced via a longer path, reading the data from the disk to the cache/SSD, and then on to the host, in order to keep a copy for future accesses during HSS mode. Either situation would reduce the speed of the read, versus normal mode (second mode), wherein it can be directly read from the disk to the host (second data interface).
Re claim 6, Hasfar 1 discloses the method of claim 4, and further discloses the following:
wherein controlling the target storage member of the electronic device switching to the corresponding data interface and/or power parameter to respond to the first or second data read/write operations from the electronic device includes: in response to the trigger signal comprising a first trigger signal of the electronic device switching from the first operation status to the second operation status, loading a boot system of the electronic device from the target storage member through the first data interface (col. 4, lines 26-44). This limitation is a conditional limitation subject to interpretation under (MPEP § 2111.04(II), and is accordingly not required to be performed. Nevertheless, in the interest of furthering compact prosecution, Examiner interprets it to mean receiving a signal to switch the system to a boot mode, and loading a boot system from memory for this mode. Hasfar discloses detecting a power up (trigger signal), which places the device into a spin-less drive boot (first application mode/first or second application status), and loads information necessary for booting (boot system) from the cache/SSD memory (via a first interface);
after the boot system completes a target task, controlling the target storage member to switch from the first data interface to the second data interface, and controlling the target storage member to switch from a first power parameter to a second power parameter, to respond to the second data read/write operations of a member of the electronic device through the second data interface (Hasfar 1, Fig. 2; col. 3, line 66 to col. 4, line 62; Hasfar 2, Fig. 3; ¶ 23, 30, and 32; claim 4). It is noted that the limitation “after the boot system completes a target task” is conditional, and is thus not required under MPEP § 2111.04(II) (see § i. above). Nonetheless, in the interest of furthering compact prosecution, Hasfar 2 discloses that the method has a spin-less boot mode (first application mode/operation status), and after booting is complete, the DSD (target storage member) switches from boot mode to normal mode, wherein in normal mode the hard disks can be accessed (Hasfar 2, Fig. 3; ¶ 23, 30, and 32; claim 4). When the DSD is in a HSS/spin-less boot mode, it has different power utilization (first/second power parameters) than when it is not. When it is in HSS/spin-less boot mode, it either fetches data from the cache/SSD, or it waits until the HDD is spun up, then fetches data from the HDD, stores it in the cache/SSD, and then forwards it from the cache/SSD to the host (either of which can be a first data interface). Conversely, if it is in normal mode, then it can be directly accessed from the HDD over the read/write interface (second data interface); (Haster 1, Fig. 2; col. 3, line 66 to col. 4, line 62;
wherein a data read/write rate of the target storage member performed through the first data interface is less than a data read/write rate of the target storage member performed through the second data interface, and power consumption of the target storage member in the first power parameter is less than power consumption of the target storage member in the second power parameter (col. 4, lines 45-62). See claim 5 above.
Re claim 7, Hasfar 1 discloses the method according to claim 6, and further comprises:
loading the boot system of the electronic device through the first data interface includes: loading the boot system of the electronic device through the first data read/write path, the first data read/write path further comprising a physical layer of the second data interface; and (Hasfar 2, Fig. 1; ¶ 23, 30, and 32; claim 4). This limitation is not required under MPEP § 2111.04(II), as noted above. Examiner interprets it to mean loading the boot mode over a first path, the first path including a controller. Hasfar 2 discloses loading the boot system from a path/interface connected to storage (either the SSD/cache or hard drive). Furthermore, all paths (first/second/third) to any of these memories go through the controller (controller core) (Fig. 1). The path includes physical channel structures (physical layer);
responding to the second data read/write operations of the member of the electronic device through the second interface includes: responding to the second data read/write operations through the second read/write path (Hasfar 1, Fig. 2; col. 3, line 66 to col. 4, line 62). This limitation is not required under MPEP § 2111.04(II), as noted above; Examiner interprets it to mean performing read/write operations over a second interface, which includes a connection to a controller. Hasfar 1 discloses in normal mode, performing reads/writes over the interface to the HDD, which also includes a controller (Fig. 2).
Re claim 8, Hasfar 1 discloses the method of claim 1, and further discloses at least one of: in response to obtaining data read/write operations from a first member and a second member of the electronic device, responding to the data read/write operations from the first member and the second member through an only data read/write channel between the controller core and the storage area of the target storage member, the first member performing the data read/write operation on a first block in the storage area, and the second member performing the data read/write operation on a second block in the storage area through the second data interface; or in response to obtaining the data read/operations from the first member and the second member of the electronic device, responding to the data read/write operation from the first member through a first data read/write channel between the controller core and the storage area of the target storage member, and responding to the data read/write operation from the second member through a second read/write channel between the controller core and the storage area of the target storage member, wherein the first member performs the data read/write operation on the first block of the storage area through the first data interface, and the second member performs the data read/write operation on the second block in the storage area through the second interface (Fig. 3). Both of these limitations are conditional, and subject to interpretation under MPEP § 2111.04(II); accordingly, they are not required. It is noted that the language “at least one of” is being interpreted as “at least one of these things would occur if the condition is met”, rather than a positive recitation of the limitations actually occurring.
Re claim 9, Hasfar 1 discloses the method of claim 1, and further discloses at least one of: in response to a failure in loading data from a first block of the storage area of the target storage member, performing address search, by the controller core of the target storage member, on a backup block of a target data file in the first block to load the target data file from the backup block (col. 4, lines 45-62). This limitation is conditional, and is thus interpreted as not being required (MPEP § 2111.04(II). In case of a read/write miss (failure in loading data), the data is instead by searching for the address in the hard disk, and executing the operation there. Hasfar discloses servicing a read/write cache/SSD miss by looking it up in the hard drive and accessing it there.
Re claim 10, Hasfar 1 discloses the following:
A storage apparatus, comprising:
a main control chip configured to control configuration parameters in one of a plurality of application modes including a first application mode and a second application mode (Figs. 4-5). Each mode (first and second application mode) is configured (configuration parameters) to access memory in a respective way. The way that storage services operations (configuration parameters) are different based on whether or not the system is in HSS mode (i.e. they are different in different modes). This process is controlled by the controller (main control chip);
a storage area having a data read and write channel with the main control chip and configured to store data content; and (Fig. 2). The controller is connected to the HDD via read/write channel 124, and connected to the cache/SSD through another connection; the cache/SSD and HDD can both be considered “a storage area” and their respective connections can be considered “ a data read and write channel”;
a first data interface and a second data interface connected to the main control chip (Fig. 2). See claim 1 above;
wherein, when the storage apparatus is in the first application mode, the storage apparatus responds to first data read/write operations through a first data read and write path formed by the second data interface, a controller core of the main control chip, the data read and write channel and the storage area (Fig. 2, solid state memory 128, read/write channel 124, disk 134; col. 4, lines 13-44). See claim 1 above. Furthermore, Applicant has not explicitly delineated the difference between the first/second data interfaces and the data read and write channel. Both appear to be part of the respective first and second read/write paths. Accordingly, Examiner interprets the read/write paths from the host to the storage apparatus as including a common host interface (the data read and write channel) as well as respective paths to the solid state memory and HDD (first/second data interfaces);
wherein, when the storage apparatus is in the second application mode, the storage apparatus responds to second data read/write operations through a second data read and write path formed by the first data interface, the controller core, the data read and write channel, and the storage area, and the first data read/write path and the second data read/write path are different from one another (Fig. 2, solid state memory 128, read/write channel 124, disk 134; col. 4, lines 45-62). See claim 1 above;
wherein the storage apparatus is associated with first configuration parameters when the storage apparatus is in the first application mode, the storage apparatus is associated with second configuration parameters when the storage apparatus is in the second application mode, and the first configuration parameters are different from the second configuration parameters (Figs. 4-5). The way that storage services operations (configuration parameters) are different based on whether or not the system is in HSS mode (i.e. they are different in different modes).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine these examples, as well as the plurality of disclosures, into a single embodiment, for the reasons noted in claim 1 above.
Re claim 14, Hasfar 1 discloses the apparatus of claim 10, and further discloses the following:
wherein the storage area includes: at least a first area block configured for a first type data read and write operation; and at least a second area block configured for a second type data read and write operation, the second type being different from the first type (Fig. 2, non-volatile cache 18, solid state memory 128, hard drive 134; Fig. 4). Applicant has not explicitly claimed what constitutes a “type” of read/write operation; accordingly, Examiner interprets a “type” to be any classification of operations, such as “reads” vs “writes”, or “accesses to cached data” vs. “accesses to non-cached data”. The DSD includes a cache/SSD (first area block) and hard drive (second area block). Accesses to cache/SSD are serviced by the first area block, and are a first type of operation; accesses to hard drive are serviced by the second area block, and are a second type of operation, different from the first;
wherein the data read and write operations supported by the storage apparatus when the storage apparatus is in different ones of the plurality of application modes (Figs. 4-5). Read and write operations of different type function differently in HSS/spin-less drive boot mode vs normal mode, such as writes directed to the hard drive being written to the hard drive in normal mode, vs being redirected to the solid state memory in HSS/spin-less drive boot mode (Figs. 4-5).
Re claim 15, Hasfar 1 discloses the apparatus of claim 14, and further discloses wherein the controller core of the main control chip has a first data read and write channel to the first area block and a second data read and write channel to the second area block to respond to the different types of data read and write operations through the first data read and write channel or the second data read and write channel; or the first area block and the second area block share a third data read and write channel between the storage area and the controller core of the main control chip, the third data read and write channel corresponding to data read and write operations for the first area block and the second area block at different times (Fig. 2). The first area block and second area block communicate with the controller core to perform respective types of operations over first and second respective channels. Hasfar discloses that the cache/SSD (first area block) and hard drive (second area block) communicate over respective channels, for read/write operations directed to them (different types of operations).
Claims 11-12 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hasfar 1 (incorporating Hasfar 2), further in view of Funaba et al (US 2001/0022739 A1)
Re claim 11, Hasfar 1 discloses the apparatus of claim 10, and further discloses the following:
the controller core stores configuration information of the storage apparatus in the plurality of application modes to cause the storage apparatus to operate in one of the plurality of application modes (Fig. 2, controller 120; col. 4, lines 26-44). The controller stores data necessary to operate in HSS/spin-less drive boot mode in the cache (col. 4, lines 26-44);
Hasfar 1 does not explicitly disclose the relative bus speeds of various storage interfaces.
Funaba discloses the following:
the main control chip includes a first interface physical layer connected to the controller core through a first bus to cause the storage to provide the first data interface; (Fig. 54; ¶ 183). The controller (controller core, main control chip) is connected via a (first) physical layer to high-speed bus1 to provide a first data interface;
the main control chip includes a second interface physical layer connected to the controller core through a second bus to cause the storage apparatus to provide the second data interface; and (Fig. 54; ¶ 183). The controller (controller core, main control chip) is connected via a (second) physical layer to lower-speed bus2 to provide a second data interface;
the first data read and write path further comprises the second interface layer, and the second data read and write path comprises the first interface physical layer (Fig. 54; ¶ 183). The first and second physical layers correspond to respective second and first data read/write paths.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the storage interfaces of Hasfar 1 to utilize different relative speed buses, as in Funaba, because it would be applying a known technique to improve a similar device in the same way. Hasfar 1 discloses a storage system including a cache/SSD and a hard drive. Funaba also discloses a storage system with a cache and an auxiliary storage device, which may be a hard drive, and which has been improved in a similar way to the claimed invention, to have the cache attached to a faster bus, and the hard drive attached to a slower bus. It would have been obvious to modify the storage device of Hasfar 1 to utilize these fast and slow buses, as in Funaba, because it would yield the predictable improvement of providing increased bandwidth to the faster device (i.e. cache/SSD).
Re claim 12, Hasfar 1 discloses the apparatus of claim 10, and further discloses wherein the main control chip includes: the controller core stores configuration information of the storage apparatus in the plurality of application modes to cause the storage apparatus to operate in one of the plurality of application modes (Fig. 2, controller 120; col. 4, lines 26-44). See claim 11 above.
Hasfar 1 does not explicitly disclose the relative bus speeds of various storage interfaces.
Funaba discloses the following:
the main control chip includes a first interface physical layer connected to the controller core through a first bus to cause the storage to provide the first data interface; (Fig. 54; ¶ 183). The controller (controller core, main control chip) is connected via a (first) physical layer to high-speed bus1 to provide a first data interface;
the main control chip includes a first bridge chip connected to the first interface physical layer through a switch to cause the storage apparatus to use the same bus between the first interface physical layer and the controller core to provide the second data interface (Fig. 54; ¶ 129 and 183). The bridge chip utilizes switches, and the second interface also utilizes at least part of the first interface. Funaba discloses that memory accesses via bus2 (second interface) are routed through the bridge to bus1, where they are provided to the controller; accordingly, bus1 (data channel) is “reused” (Fig. 54; ¶ 183). Additionally, the bridge chip is a semiconductor chip, comprising transistors (switches). Furthermore, Funaba implements various signaling using MOS transistor switches (¶ 129).
wherein the first data read and write path further comprises the first interface physical layer, the switch, and the first bridge chip, and the second data read and write path further comprises the first interface physical layer (Fig. 54; ¶ 129 and 183). Read/write operations are serviced along a path that includes the controller core, the first interface physical layer, the switch, and the first bridge chip. Memory accesses from the hard drives pass over the bridge circuit (bridge chip and switch) as well as bus1 (first interface physical layer) and to the controller core (Fig. 54; ¶ 183). As noted above, the various signals in the system are implemented using MOS switch transistors (¶ 129).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Hasfar and Funaba, for the reasons noted in claim 11 above.
Re claim 16, Hasfar 1 discloses the apparatus of claim 10; accordingly, it also discloses an electronic device implementing similar functionality, as in claim 16 (See Hasfar 1, Abstract). Hasfar 1 further discloses that the apparatus can be a computer; while it is well known in the art that a computer includes a motherboard, this is not explicitly stated in Hasfar. Accordingly, in the interest of furthering compact prosecution, Examiner has provided Funaba.
Funaba discloses a motherboard (Fig. 1, motherboard 101). The computing system contains a motherboard.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the computer of Hasfar 1 to include a motherboard, as in Funaba, because it would be combining prior art elements according to known methods to yield predictable results. Hasfar 1 and Funaba disclose all the elements of the claimed invention, with the only difference between the claimed invention and the prior art being lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements, as claimed by known methods, and that in combination each element merely performs the same function as it does separately (i.e. the computer of Hasfar 1 would perform the same functions with the inclusion of a motherboard, and likewise, the motherboard of Funaba would still perform the same motherboard functions if it were part of the particular computing system of Hasfar 1). One of ordinary skill would have recognized that the results of combining a motherboard into a computer would be predictable, as it is extremely common for computers to have motherboards.
Re claim 17, Hasfar 1 and Funaba disclose the apparatus of claim 16, and Hasfar 1 further discloses a power supply management controller configured to control power parameters of the storage apparatus […] wherein for each application mode, the storage apparatus is powered selectively […]; or the motherboard includes a first interface pin matching the first data interface and a second interface pin matching the second data interface of the storage apparatus, the first interface pin being welded with a metal pin of the first data interface, the second interface pin being welded with a metal pin of the second data interface (Fig. 1; col. 2, lines 34-52). The DSD performs power management functions (power supply management controller configured to control power parameters) in each mode.
Funaba further discloses to control power parameters of the storage through a first power supply circuit connected to the first data interface and/or a second power supply circuit connected to the second data interface, wherein […] the storage apparatus is powered selectively via the first power supply circuit or via the second power supply circuit (Abstract). The various memories are connected to various data wirings (interfaces) and various power wirings (first power supply circuit and/or second power supply circuit) from the motherboard.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to power the computing system using multiple parallel power paths (power supplies), as in Funaba, because Funaba suggests that this would stabilize the supply of power (Abstract).
Re claims 18-19, Hasfar 1 and Funaba disclose the apparatuses of claims 11-12 above, respectively; accordingly, they also disclose devices implementing the same functionality, as in claims 18-19, respectively (see Hasfar 1, abstract).
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
ACKNOWLEDGEMENT OF ISSUES RAISED BY THE APPLICANT
Response to Amendment
Applicant’s arguments with respect to claims 1-20 filed on 10/27/2025 have been fully considered.
As required by M.P.E.P. § 707.07(f), a response to these arguments appears below.
ARGUMENTS CONCERNING 35 USC § 112(b) REJECTIONS
Re claims 1-20, Examiner notes Applicant’s amended claims dated 10/27/2025. In view of the amended claims, Examiner’s prior rejections under 35 USC § 112(b) have been rendered moot, and are accordingly withdrawn.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Claims must be given the broadest reasonable interpretation during examination and limitations appearing in the specification but not recited in the claim are not read into the claim (See M.P.E.P. 2111 [R-1]).
Re claims 1, 10, and 16, Applicant argues that Hasfar 1, Hasfar 2, and Funaba do not disclose the claimed invention, for 2 reasons.
First, Applicant “notes that Hasfar 1 discloses separate SSD and rotational service paths in the solid-state hybrid DSD”. Examiner notes that this does not constitute an explicit argument against applicability of the Hasfar 1 reference to the claimed invention; nevertheless, in the interest of furthering compact prosecution, Examiner clarifies that the current claim language “the storage area” is broad enough to potentially encompass both the solid state memory and the HDD of Hasfar 1; accordingly, the data may be considered to be accessed in “the storage area” in each mode, even if it may be accessed via different copies in different locations of the storage area. Examiner contacted Applicant’s attorney Li Jiang (74191) to suggest further clarification to limit the scope of “the storage area”, but no amendment was ultimately agreed to.
Second, Applicant argues that Hasfar 1, Hasfar 2, and Funaba do not disclose that the target storage member responds to read/write operations using different read/write paths, selectively, via either the first data interface or the second data interface. In response, Applicant’s second argument has been fully considered, but is not deemed persuasive, for 2 reasons. First, while Applicant has claimed that the first and second read/write paths are different from one another, this does not mean that they must have zero overlap between them. For instance, the paths may share a common interface between the host to the controller, but then split off and access memory utilizing different interfaces, as in Hasfer 1. The overall paths are different even if some portions are shared. Second, even assuming the paths did need to be completely separate, Hasfar 1 shows a path (first path) from the controller to the solid state memory over a first interface that is completely separate from a path (second path) from the controller to the HDD over a second interface.
Re claims 2-9, 11-15, and 17-19, Applicant argues that the claims are allowable by virtue of their dependence upon one of claims 1, 10, and 16 above, respectively. Accordingly, Applicant is directed to Examiner’s comments regarding claims 1, 10, and 16 above, respectively.
Re claim 20, the claim is objected to as dependent upon a rejected base claim, as noted above.
All arguments by the Applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated 10/27/2025.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Klapman (US 2023/0004290 A1). Discloses sending power and data to storage over a common USB data interface (¶ 50).
Per the instant office action, claims 1-19 have received an action on the merits and are subject to a final rejection. Claim 20 is objected to, as noted above.
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/CRAIG S GOLDSCHMIDT/Primary Examiner, Art Unit 2132