DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitation “wherein the first and second parasitic loading values are different” in lines 9-10 of the claim. However, this subject matter is not disclosed in the original specification.
Because the limitation “wherein the first and second parasitic loading values are different” of claim 1 was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention, this limitation is considered new matter.
Claims 10 and 16 recite the limitation “wherein the first and second clock signal taps may be unbalanced” in lines 10-11 and lines 13-14 of the claims, respectively. However, this subject matter is not disclosed in the original specification.
Because the limitation “wherein the first and second clock signal taps may be unbalanced” of claims 10 and 16 was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention, this limitation is considered new matter.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kuttappa et al. (“Robust Low Power Clock Synchronization for Multi-Die Systems”; “Kuttappa”; reference of record) in view of Johnson (US 11,226,767; reference of record).
Regarding claim 1, Kuttappa teaches an apparatus (figures 1-2) comprising:
a base die (silicon interposer) that includes resonant rings of respective rotary oscillators (See five rings in figure 1), wherein the resonant rings of different rotary oscillators are shorted to one another to form a rotary oscillator array (ROA in figure 5 comprising 5 rings of oscillators); and
a first die (core1) and a second die (core2) coupled to the base die (silicon interposer), wherein the first die (core1) is to tap, at a first parasitic loading value (parasitic loading is inherent), a first clock signal from the ROA and wherein the second die (core2) is to tap, at a second parasitic loading value (parasitic loading is inherent), a second clock signal from the ROA (Paragraph 3 under the heading “I. Introduction” teaches the multiple dies being synchronized with tapped clocks from the rotary oscillator array).
Kuttappa fails to teach wherein the first die transmits data to the second die based on the first clock signal; and wherein the second die receives the data based on the second clock signal.
However, it is well-known to those of ordinary skill in the art to utilize synchronized clocks in a multi-die system for coordinating die-to-die communication. For example, see col. 13, lines 14-46 and claim 13 of Johnson.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the synchronized clocks in the multi-die system of Kuttappa for coordinating die-to-die communication because such a modification would have been implementing a well-known application of synchronized clocks in a multi-die system.
As for claim 2, Kuttappa teaches wherein the resonant rings of the respective rotary oscillators include a first ring and a second ring that are cross-coupled to one another (See rings in figure 1), wherein the rotary oscillators further include one or more pairs of cross-coupled inverters that are coupled between the first ring and the second ring (See cross-coupled inverters in figure 2).
As for claim 3, Kuttappa teaches the first clock signal and the second clock signal being synchronized (Paragraph 3 under the heading “I. Introduction” teaches the multiple dies being synchronized with tapped clocks from the rotary oscillator array), but fails to teach wherein the first clock signal has a same phase as the second clock signal.
However, it is well-known to those of ordinary skill in the art to configure synchronized clocks with the same phase.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize clocks with the same phase as the synchronized clocks of Kuttappa because such a modification would have been implementing a well-known example of synchronized clocks.
As for claim 4, Kuttappa teaches wherein the rotary oscillators are rotary traveling wave oscillators (Paragraph 3 under the heading “I. Introduction”).
As for claim 5, Kuttappa teaches the first clock signal and the second clock signal being synchronized (Paragraph 3 under the heading “I. Introduction” teaches the multiple dies being synchronized with tapped clocks from the rotary oscillator array), but fails to teach wherein the second clock signal is ahead in phase by 45 to 135 degrees compared to the first clock signal.
However, it is well-known to those of ordinary skill in the art to configure synchronized clocks with phases having a difference of 45 to 135 degrees.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize clocks having a phase difference of 45 to 135 degrees as the synchronized clocks of Kuttappa because such a modification would have been implementing a well-known example of synchronized clocks.
Regarding claim 6, Kuttappa modified by Johnson teaches wherein the data is transmitted via a communication bus with multiple channels (communication between different dies core1-core4 will use different channels) that use respective pairs of tap points (see tapping point pairs in figure 1b), but fails to expressly teach wherein the respective pairs of tap points have different phase differences between the first and second clock signals.
However, it is well-known to those of ordinary skill in the art to configure synchronized clocks with phase differences.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize clocks having phase differences as the synchronized clocks of Kuttappa because such a modification would have been implementing a well-known example of synchronized clocks.
Regarding claim 7, Kuttappa teaches the apparatus of claim 1, as detailed above, but fails to teach wherein the rotary oscillators are rotary standing wave oscillators.
However, it is well-known to those of ordinary skill in the art to embody a rotary oscillator as a rotary standing wave oscillator.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the rotary oscillator of Kuttappa as a rotary standing wave oscillator because such a modification would have been a replacement with a well-known rotary oscillator configuration.
Regarding claim 10, Kuttappa teaches an apparatus (figures 1-2) comprising:
a base die (silicon interposer) that includes a resonant ring structure of a rotary oscillator (See rings of rotary oscillator in figure 1);
a first die (core1) coupled to the base die, wherein the first die (core1) is formed above a resonant ring (on interposer) and taps a first clock signal from the resonant ring (See tapping points in figure 1b),
a second die (core4) coupled to the base die, wherein the second die (core4) is formed above the resonant ring (on interposer) and taps a second clock signal from the resonant ring (See tapping points in figure 1b).
Kuttappa fails to teach wherein the first die includes transmit circuitry that transmits data over a communication bus to the second die based on the first clock signal; and wherein the second die includes receive circuitry coupled to the communication bus that receives the data based on the second clock signal.
However, it is well-known to those of ordinary skill in the art to utilize synchronized clocks in a multi-die system for coordinating die-to-die communication. For example, see col. 13, lines 14-46 and claim 13 of Johnson.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the synchronized clocks in the multi-die system of Kuttappa for coordinating die-to-die communication because such a modification would have been implementing a well-known application of synchronized clocks in a multi-die system.
As for claim 11, Kuttappa modified by Johnson teaches wherein the transmit circuitry is above a first long edge of the resonant ring structure and is to tap the first clock signal from the first long edge, and wherein the receive circuitry is above a second long edge of the resonant ring structure and is to tap the second clock signal from the second long edge (Core1 is along a first long edge and core 2 is along a second long edge in figure 1).
As for claim 12, Kuttappa teaches wherein the rotary oscillator is a rotary traveling wave oscillator (Paragraph 3 under the heading “I. Introduction”).
Regarding claim 13, Kuttappa teaches the apparatus of claim 12, as detailed above, but fails to teach wherein the rotary oscillator further includes a clock recovery circuit coupled to a first ring and a second ring of the resonant ring structure to generate a square wave signal as the clock signal.
However, it is well-known to those of ordinary skill in the art to utilize a clock recovery circuit coupled to an oscillator for generating a square wave signal.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a clock recovery circuit to the oscillator output of Kuttappa because such a modification would have been an addition of a well-known oscillator output circuit.
As for claim 14, Kuttappa teaches the first clock signal and the second clock signal being synchronized (Paragraph 3 under the heading “I. Introduction” teaches the multiple dies being synchronized with tapped clocks from the rotary oscillator array), but fails to teach wherein the second clock signal is ahead in phase by 45 to 135 degrees compared to the first clock signal.
However, it is well-known to those of ordinary skill in the art to configure synchronized clocks with phases having a difference of 45 to 135 degrees.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize clocks having a phase difference of 45 to 135 degrees as the synchronized clocks of Kuttappa because such a modification would have been implementing a well-known example of synchronized clocks.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kuttappa in view of Johnson and Abbasalizadeh et al. (“Phase Transition Analysis of Dual-Mode Standing-Rotary Traveling-Wave Oscillator”; “Abbasalizadeh”; reference of record).
Regarding claim 8, Kuttappa teaches the apparatus of claim 1, as detailed above, but fails to teach wherein at least one of the rotary oscillators is operable in a traveling wave mode and a standing wave mode, and wherein the rotary oscillators include one or more switches coupled between the first ring and the second ring of the respective rotary oscillators, and wherein the apparatus further comprises control circuitry to control the switches to be open when the respective rotary oscillator is in the traveling wave mode, and control the switches to have a selected one of the switches to be closed when the respective rotary oscillator is in the standing wave mode.
However, it is well-known to those of ordinary skill in the art to switch a rotary oscillator between a traveling wave mode and a standing wave mode. For example, see figure 1 and associated description of Abbasalizadeh.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to switch the rotary oscillator of Kuttappa between a standing wave mode and a traveling wave mode because such a modification would have been implementing a well-known rotary oscillator configuration.
Claims 9 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kuttappa in view of Johnson and Wood (US 2008/0260049; reference of record).
Regarding claim 9, Kuttappa teaches the apparatus of claim 1, as detailed above, but fails to teach wherein the first die includes one or more serializers to serialize the data for transmission based on the first clock signal, and wherein the second die includes one or more deserializers to deserialize the data.
However, it is well-known to those of ordinary skill in the art to utilize serializers and deserializers in a data communication system. For example, see figure 1A of Wood.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add serializers and deserializers to the data communication system of Kuttappa because such a modification would have been additions of well-known data communication components.
As for claim 15, Kuttappa teaches the apparatus of claim 14, as detailed above, but fails to teach wherein the transmit circuitry includes one or more serializers to serialize the data, based on the first clock signal, for transmission over the communication bus, and wherein the receive circuitry includes one or more deserializers to deserialize the data based on the second clock signal.
However, it is well-known to those of ordinary skill in the art to utilize serializers and deserializers in a data communication system. For example, see figure 1A of Wood.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add serializers and deserializers to the data communication system of Kuttappa because such a modification would have been additions of well-known data communication components.
Regarding claim 16, Kuttappa teaches a computer system, comprising: a multi-die system (Figures 1-2) that includes:
a base die (silicon interposer) that includes a resonant ring structure of a traveling wave rotary oscillator (RTWO) array (figure 1; Paragraph 3 under the heading “I. Introduction”),
a first die (core 1) coupled to the base die, wherein the first die taps a first clock signal from the resonant ring structure (See tapping points in figure 1b), and
a second die (core4) coupled to the base die, wherein the second taps a second clock signal from the resonant ring structure (See tapping points in figure 1b); and
one or more memory modules (DRAM) coupled to the first die.
Kuttappa fails to teach wherein the first die includes transmit circuitry that serializes data based on the first clock signal; and wherein the second die includes receive circuitry that deserializes the data based on the second clock signal, and wherein the second clock signal has a different phase than the first clock signal.
However, it is well-known to those of ordinary skill in the art to utilize synchronized clocks in a multi-die system for coordinating die-to-die communication. For example, see col. 13, lines 14-46 and claim 13 of Johnson.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the synchronized clocks in the multi-die system of Kuttappa for coordinating die-to-die communication because such a modification would have been implementing a well-known application of synchronized clocks in a multi-die system.
Furthermore, it is well-known to those of ordinary skill in the art to configure synchronized clocks with phase differences.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize clocks having phase differences as the synchronized clocks of Kuttappa because such a modification would have been implementing a well-known example of synchronized clocks.
Lastly, it is well-known to those of ordinary skill in the art to utilize serializers and deserializers in a data communication system. For example, see figure 1A of Wood.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add serializers and deserializers to the data communication system of Kuttappa because such a modification would have been additions of well-known data communication components.
Regarding claim 17, Kuttappa modified by Johnson teaches wherein the data is transmitted via a communication bus with multiple channels (communication between different dies core1-core4 will use different channels) that use respective pairs of tap points (see tapping point pairs in figure 1b), but fails to expressly teach wherein the respective pairs of tap points have different phase differences between the first and second clock signals.
However, it is well-known to those of ordinary skill in the art to configure synchronized clocks with phase differences.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize clocks having phase differences as the synchronized clocks of Kuttappa because such a modification would have been implementing a well-known example of synchronized clocks.
Regarding claims 18 and 19, Kuttappa teaches the system of claim 16, as detailed above, but fails to teach wherein the transmit circuitry and the receive circuitry are to tap the respective first and second clock signals from a same ring of the resonant ring structure or from different rings of the resonant ring structure.
However, as would have been recognized by one of ordinary skill in the art, as long as the first and second clocks are synchronized, the resonant ring structure of Kuttappa from which the first and second clocks are tapped does not affect the operation of the multi-die system of Kuttappa.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to tap the first and second clock signals from a same ring of the resonant ring structure or from different rings of the resonant ring structure of Kuttappa because such a modification would not have affected the operation of the multi-die system of Kuttappa.
As for claim 20, Kuttappa modified by Johnson teaches wherein the transmit circuitry is above a first long edge of the resonant ring structure and is to tap the first clock signal from the first long edge, and wherein the receive circuitry is above a second long edge of the resonant ring structure and is to tap the second clock signal from the second long edge (Core1 is along a first long edge and core 2 is along a second long edge in figure 1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEVI GANNON whose telephone number is (571)272-7971. The examiner can normally be reached 7:00AM-4:30PM.
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/LEVI GANNON/Primary Examiner, Art Unit 2849 January 16, 2026