Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
DETAILED ACTION
Status
This instant application No. 18/821913 has claims 1-20 pending. The effective filing date of this application is 03/21/2012.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 10 of U.S. Patent No. 12,079,060 and over claims 21 and 31 of the U.S. Patent No. 11,507,173. Although the claims at issue are not identical, they are not patentably distinct from each other.
For the purpose of illustration, only claim 1 of the instant application is compared with claim 1 of the US Patent 12,079, 060, and claim 1 of the instant application is compared with claim 21 of the US Patent 11,507,173 in the following table (underlining is used to indicate conflicting limitations):
Instant application
US Patent 12,079,060
Claim 1. A storage device comprising:
a first device configured to store data in a volatile manner;
a second device configured to store data in a nonvolatile manner;
a connector through which a first power is supplied from outside of the storage device;
a first circuit configured to generate a second power that is different from the first power;
a second circuit configured to supply a third power based on either the first power or the second power depending on a voltage level of the first power; and
a control circuit configured to:
start an operation of saving data stored in the first device to the second device using the third power based on the first power, after the voltage level of the first power decreases from a first level to a second level that is lower than the first level, and
continue the operation of saving the data stored in the first device to the second device using the third power based on the second power, after the voltage level of the first power further decreases from the second level to a third level that is lower than the second level.
Claim 1. A memory system comprising:
a first memory configured to store data in a volatile manner;
a second memory configured to store data in a nonvolatile manner;
a battery configured to be charged by a first power from outside of the memory system and generate a second power;
a power supply circuit configured to supply a third power based on either the first power or the second power depending on a voltage level of the first power; and
a control circuit configured to:
start an operation of saving data stored in the first memory to the second memory using the third power based on the first power, when the voltage level of the first power drops to a first value, and
continue the operation of saving the data stored in the first memory to the second memory using the third power based on the second power, when the voltage level of the first power drops further to a second value that is lower than the first value.
Instant application
US Patent 11,507,173
Claim 1. A storage device comprising:
a first device configured to store data in a volatile manner;
a second device configured to store data in a nonvolatile manner;
a connector through which a first power is supplied from outside of the storage device;
a first circuit configured to generate a second power that is different from the first power;
a second circuit configured to supply a third power based on either the first power or the second power depending on a voltage level of the first power; and
a control circuit configured to:
start an operation of saving data stored in the first device to the second device using the third power based on the first power, after the voltage level of the first power decreases from a first level to a second level that is lower than the first level, and
continue the operation of saving the data stored in the first device to the second device using the third power based on the second power, after the voltage level of the first power further decreases from the second level to a third level that is lower than the second level.
Claim 21. A memory system comprising:
a first memory configured to store data;
a second memory different from the first memory and configured to store data in a nonvolatile manner;
a connector through which a first power is supplied from outside of the memory system;
a battery configured to be charged by a first power and generate a second power;
a first circuit configured to monitor a level of a voltage of the first power supplied from outside of the memory system via the connector;
a power supply circuit configured to generate a third power from either the first power or the second power depending on the level of the voltage monitored by the first circuit; and
a control circuit configured to:
start an operation of saving data stored in the first memory to the second memory using the third power generated from the first power, in response to the monitored level of voltage of the first power drops to a first value, and
continue the operation of saving the data stored in the first memory to the second memory using the third power generated from the second power, in response to the monitored level of voltage of the first power dropping further to a second value that is lower than the first value.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 7, 8, 10-15, 17 ,18 and 20 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Sweere et al (2010/0008175) hereinafter Sweere in view of Ishikawa et al (2008/0086659) hereinafter Ishikawa.
Regarding claim 1, Sweere teaches A storage device (Sweere: Fig. 2) comprising:
a first device configured to store data in a volatile manner (Sweere: Fig. 2: volatile memory 204);
a second device configured to store data in a nonvolatile manner (Sweere: Fig. 2: Non-volatile memory 206);
a connector through which a first power is supplied from outside of the storage device (Sweere: Fig. 2: the external power source supplies the power the host system through the interface 202);
Sweere does not explicitly teach continue the operation of saving the data stored in the first device to the second device using the third power based on the second power, after the voltage level of the first power further decreases from the second level to a third level that is lower than the second level.
However, Ishikawa teaches continue the operation of saving the data stored in the first device to the second device using the third power based on the second power, after the voltage level of the first power further decreases from the second level to a third level that is lower than the second level (Ishikawa: [0014]: “a power failure detecting signal when the power source voltage is below a second threshold voltage that is lower than the first threshold voltage; and a control section adapted to start saving of the data in the volatile memory into the nonvolatile memory when the detecting circuit has output the momentary interruption detecting signal, continue save of the data, and carry out a predetermined shutdown processing when the detecting circuit has output the power failure detecting signal after the detecting circuit has output the momentary interruption detecting signal”).
Disclosures by Sweere and Ishikawa are analogous because they are in the same field
of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art at the time of the invention to incorporate saving data from volatile memory to
nonvolatile memory using backup power source when detecting a power failure disclosed by
Sweere to include saving data when the power from external power drops further to a second
threshold value disclosed by Ishikawa. The motivation for saving data when the power from
external power drops further to a second threshold value by [0012] of Ishikawa is for increasing
the amount of data to be saved into the nonvolatile memory when power is off.
Regarding claim 11, these claims limitations are significantly similar to those of claim 1, and, therefore, are rejected on the same grounds.
Regarding claim 2, Sweere combined further teaches The storage device according to claim 1, wherein a first voltage level of the first power before the control circuit continues the operation is different from a second voltage level of the second power after the control circuit continues the operation (Sweere: [0081]: "The power supplied by the super-capacitors 514 may sustain the memory module 500 for up to several seconds (e.g., 1 to 20 seconds) in the event of a system power failure. This may be an adequate sustain time to perform complete transfer of data from the volatile memory 504 to the non-volatile memory 514").
Regarding claim 12, these claims limitations are significantly similar to those of claim 2, and, therefore, are rejected on the same grounds.
Regarding claim 3, Sweere combined further teaches The storage device according to claim 1, wherein a first voltage level of the third power before the control circuit continues the operation is different from a second voltage level of the third power after the control circuit continues the operation (Sweere: [0044]: “If a power failure event (e.g., low voltage level) is detected, the backup power source provides sufficient power long enough (e.g., 8 to 10 seconds) to backup data from the volatile memory devices to on-board non-volatile memory devices”).
Regarding claim 13, these claims limitations are significantly similar to those of claim 3, and, therefore, are rejected on the same grounds.
Regarding claim 4, Sweere combined further teaches The storage device according to claim 1, further comprising: the connector is configured to receive from a host device a first command requesting to store data to the second device and a second command requesting to read data from the second device (Sweere: Fig.2: interface to host 202 to interface to/from host system).
Regarding claim 5, Sweere combined further teaches The storage device according to claim 1, wherein the data saved from the first device to the second device includes user data that are input from an external device (Sweere: Fig. 1: [0042]: "cache memory storage 106 which may be used to temporarily store data as it is transferred from the host computer 102 to the RAID 108").
Regarding claim 15, these claims limitations are significantly similar to those of claim 5, and, therefore, are rejected on the same grounds.
Regarding claim 7, Ishikawa combined further teaches The storage device according to claim 1, wherein the control circuit includes a processor configured to perform starting and continuing the operation (Ishikawa: Fig. 1: Control Circuit Board includes the processor 11).
Disclosures by Sweere and Ishikawa are analogous because they are in the same field
of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art at the time of the invention to incorporate saving data from volatile memory to nonvolatile memory using backup power source when detecting a power failure disclosed by Sweere to include saving data when the power from external power drops further to a second threshold value disclosed by Ishikawa. The motivation for saving data when the power from external power drops further to a second threshold value by [0012] of Ishikawa is for increasing the amount of data to be saved into the nonvolatile memory when power is off.
Regarding claim 17, these claims limitations are significantly similar to those of claim 7, and, therefore, are rejected on the same grounds.
Regarding claim 8, Sweere combined further teaches The storage device according to claim 1, wherein both the first and second devices are disposed separately from the control circuit (Sweere: Volatile memory device 204 and non-volatile memory device 206 are separated from the Backup/Restore Logic Device).
Regarding claim 18, these claims limitations are significantly similar to those of claim 8, and, therefore, are rejected on the same grounds.
Regarding claim 10, Sweere combined further teaches The storage device according to claim 1, wherein the first device includes a DRAM (Sweere: [0046]: "The memory module 200 may also include one or more onboard volatile memory devices 204 (e.g., double data rate (DDR) synchronous dynamic random access memory (DRAM)").
Regarding claim 20, these claims limitations are significantly similar to those of claim 10, and, therefore, are rejected on the same grounds.
Regarding claim 14, Sweere combined further teaches The method according to claim 11, wherein the first power is supplied from a host device via a connector connected to the storage device (Sweere: Fig. 2: the External power Source supplies power to the memory module through the interface 202).
Claims 6 and 16 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Sweere et al (2010/0008175) hereinafter Sweere in view of Ishikawa et al (2008/0086659) hereinafter Ishikawa, as applied to claims 1 and 11 respectively above, and further in view
of Okawa (2012/0221801) hereinafter Okawa.
Regarding claim 6, Sweere and Ishikawa do not explicitly teach the current limitations
of claim 6.
However, Okawa teaches The storage device according to claim 1, wherein the data saved from the first device to the second device includes management data that are managed by the storage device (Okawa: [0068]: "In the case in which a power outage
occurs in the case of the state (3), the data and the management data that have been
stored into the cache memory 3 is transferred to the flash memory device 4, and is stored
into the flash memory device 4").
Disclosures by Sweere, Ishikawa and Okawa are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art at the time of the invention to incorporate saving data from volatile memory to nonvolatile memory using backup power source when detecting a power failure disclosed by
Sweere/Ishikawa to include saving management data when detecting low level of power source disclosed by Okawa. The motivation for saving management data when detecting low level of power source by [0006] of Okawa is for data reliability and data usability.
Regarding claim 16, these claims limitations are significantly similar to those of claim 6, and, therefore, are rejected on the same grounds.
Claims 9 and 19 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Sweere et al (2010/0008175) hereinafter Sweere in view of Ishikawa et al (2008/0086659) hereinafter Ishikawa, as applied to claims 1 and 11 respectively above, and further in view of Trantham (2010/0332859) hereinafter Trantham.
Regarding claim 9, Sweere and Ishikawa do not teach the current limitation of claim 9.
However, Trantham teaches The storage device according to claim 1, wherein the second device includes a NAND type flash memory (Trantham: [0017]: "nonvolatile solid-state data memory devices include, but are not limit to, NAND flash").
Disclosures by Sweere, Ishikawa and Trantham are analogous because they are in the
same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art at the time of the invention to incorporate saving data from volatile memory to
nonvolatile memory using backup power source when detecting a power failure disclosed by
Sweere/Ishikawa to include saving management data when detecting low level of power source
disclosed by Trantham. The motivation for saving management data when detecting low level of
power source by [0010] of Trantham is for backing up data when system power is lost.
Regarding claim 19, these claims limitations are significantly similar to those of claim 9, and, therefore, are rejected on the same grounds.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. These references include:
Nishioka (2010/0237913), which teaches an electronic device includes a first reset signal generator arranged to output a first reset signal when a power supply voltage becomes lower than or equal to a first threshold, a second reset signal generator arranged to output a second reset signal when the power supply voltage becomes lower than or equal to a second threshold lower than the first threshold. The threshold values of the power supply voltage, and timings of outputting a signal, which becomes a trigger in saving the data, and the reset signal are shifted to ensure the period for saving the data threshold values of the power supply voltage, and timings of outputting a signal, which becomes a trigger in saving the data, and the reset signal are shifted to ensure the period for saving the data in a volatile storage device to a nonvolatile storage device and resetting the device when a power supply is shut off.
Trantham (2010/0332858), which teaches systems and methods for use with power control features that providing mass-storage memory that is able to retain stored data when the computer system is powered down. An operating power circuit provides operating power to memories and a control circuit. the operating power circuit receives its power from a host-system power source. When system power is lost, the operating power circuit receives its power from a backup power circuit. The backup power circuit includes an energy-storage circuit, also referred to as a power-reservoir circuit, with a capacitor acting as an energy-storage device. The capacitor is designed to hold sufficient energy to provide substantially all of the primary-operating power to the memory circuits during a minimum time period sufficient to permit transfer of pertinent data from the volatile memory circuit to the nonvolatile memory circuit.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAN V DOAN whose telephone number is (571)270-7250. The examiner can normally be reached Monday, Wednesday and Thursday from 10:45 AM to 4:45PM EST.
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/HAN V DOAN/Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137