DETAILED ACTION
Status of the Claims
The filing dated 9/2/24 is entered. Claims 1-8 are pending.
Foreign Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statements
The information disclosure statement (IDS) submitted on 9/2/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang, KR-20210154829.
In regards to claim 1, Huang discloses a three-dimensional flash memory based on a stack process (Par. 0005 stacked 3D NAND), comprising: a first memory block (Fig. 1A, 108 memory stack) including first vertical channel structures (Fig. 1A, 132 memory strings) formed to extend in a vertical direction (Fig. 1A, 132 memory strings) on a first substrate (Fig. 1A, 102 substrate); a second memory block (Fig. 1A, 108 memory stack) including second vertical channel structures (Fig. 1A, 138 bit line) formed to extend the vertical direction (Fig. 1A, 138 memory strings) on a second substrate (Fig. 1A, 104 substrate); and a connection pad (Fig. 1A, 142+144 bit bonding contact) connecting the first memory block (Fig. 1A, 108 memory stack) and the second memory block (Fig. 1A, 108 memory stack) arranged such that at least one first bit line (Fig. 1A, 134 bit line) connected to the first vertical channel structures (Fig. 1A, 132 memory strings) and at least one second bit line (Fig. 1A, 138 bit line) connected to the second vertical channel structures (Fig. 1A, 138 bit line) face each other.
In regards to claim 2, Huang discloses three-dimensional flash memory based on a stack process (Par. 0005 stacked 3D NAND), comprising: a first memory block (Fig. 1A, 108 memory stack) including first vertical channel structures (Fig. 1A, 132 memory strings) formed to extend in a vertical direction (Fig. 1A, 132 memory strings) on a first substrate (Fig. 1A, 102 substrate); a second memory block (Fig. 1A, 108 memory stack) including second vertical channel structures (Fig. 1A, 138 bit line) formed to extend in the vertical direction (Fig. 1A, 138 bit line) on a second substrate (Fig. 1A, 104 substrate); and a connection pad (Fig. 1A, 142+144 bit bonding contact) connecting the first memory block (Fig. 1A, 108 memory stack) and the second memory block (Fig. 1A, 108 memory stack) arranged such that the first substrate (Fig. 1A, 102 substrate) and the second substrate (Fig. 1A, 104 substrate) face each other.
In regards to claim 3, Huang discloses the connection pad (Fig. 1A, 142+144 bit bonding contact) includes a connection wiring line (Fig. 1A, 140 conductive routing) of the at least one first bit line (Fig. 1A, 134 bit line) connected to the first vertical channel structures (Fig. 1A, 132 memory strings) and a connection wiring line (Fig. 1A, 146 conductive routing) of the at least one second bit line (Fig. 1A, 138 bit line) connected to the second vertical channel structures (Fig. 1A, 138 bit line).
In regards to claim 4, Huang discloses the connection pad (Fig. 1A, 142+144 bit bonding contact) is commonly provided with the connection wiring line (Fig. 1A, 140 conductive routing) of the at least one first bit line (Fig. 1A, 134 bit line) connected to the first vertical channel structures (Fig. 1A, 132 memory strings) and the connection wiring line (Fig. 1A, 146 conductive routing) of the at least one second bit line (Fig. 1A, 138 bit line) connected to the second vertical channel structures (Fig. 1A, 138 bit line).
In regards to claim 5, Huang discloses the connection pad (Fig. 1A, 142+144 bit bonding contact) connects the first memory block (Fig. 1A, 108 memory stack) and the second memory block (Fig. 1A, 108 memory stack) to each other through bonding or connects the first memory block (Fig. 1A, 108 memory stack) and the second memory block (Fig. 1A, 108 memory stack) to each other through a through silicon via (TSV) (Par. 0048 using TSV).
In regards to claim 6, Huang discloses the connection pad (Fig. 1A, 142+144 bit bonding contact) includes a connection wiring line (Fig. 1A, 140 conductive routing) of the at least one first bit line (Fig. 1A, 134 bit line) connected to the first vertical channel structures (Fig. 1A, 132 memory strings) and a connection wiring line (Fig. 1A, 146 conductive routing) of the at least one second bit line (Fig. 1A, 138 bit line) connected to the second vertical channel structures (Fig. 1A, 138 bit line).
In regards to claim 7, Huang discloses the connection pad (Fig. 1A, 142+144 bit bonding contact) is commonly provided with the connection wiring line (Fig. 1A, 140 conductive routing) of the at least one first bit line (Fig. 1A, 134 bit line) connected to the first vertical channel structures (Fig. 1A, 132 memory strings) and the connection wiring line (Fig. 1A, 146 conductive routing) of the at least one second bit line (Fig. 1A, 138 bit line) connected to the second vertical channel structures (Fig. 1A, 138 bit line).
In regards to claim 8, Huang discloses the connection pad (Fig. 1A, 142+144 bit bonding contact) connects the first memory block (Fig. 1A, 108 memory stack) and the second memory block (Fig. 1A, 108 memory stack) to each other through bonding or connects the first memory block (Fig. 1A, 108 memory stack) and the second memory block (Fig. 1A, 108 memory stack) to each other through a through silicon via (TSV) (Par. 0048 using TSV).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY A ALMEIDA whose telephone number is (571)270-3143. The examiner can normally be reached M-Th 9AM-730PM.
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/CORY A ALMEIDA/Primary Examiner, Art Unit 2628 8/24/26
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