DETAILED ACTION
This Office Action is in response to Application filed 02 September 2024.
Claims 1-19 are pending. The claims have been considered and examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim(s) 7, 14, 15, 17 is/are objected to because of the following informalities:
Claim 7 cites “a second timing module”, when there is no “a first timing module” in claim 7 or the claim from which it depends, claim 1.
Claim 14 cites “a second count value”, when there is no “a first count value” in claim 14 or the claims from which it depends, claims 12, 10, 9, 8, 7 and 1.
Claim 14 cites “a second threshold”, when there is no “a first threshold” in claim 14 or the claims from which it depends, claims 12, 10, 9, 8, 7 and 1.
Claim 15 cites “a third count value”, when there is no “a second count value” or “a first count value” in claim 15 or the claims from which it depends, claims 10, 9, 8, 7, and 1.
Claim 17 cites “a third threshold”, when there is no “a second threshold” or “a first threshold” in claim 17, or the claims form which it depends, claims 16, 15, 10, 9, 8, 7, and 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 18, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Song, U.S. Patent App. Pub. 2021/0141687, hereinafter referred to as “Song”.
Referring to claim 1, Song discloses a semiconductor with error check and scrub, ECS (See paragraph 0005). - An error check and scrub (ECS) circuit, comprising
Song discloses an ECS control circuit, a ECS command generation circuit, an address counter, and error log storage circuit (See paragraphs 0037, 0040, and 0044). - an ECS control module, a command generation module, an address counting module, and an error tracking and recording module,
Song discloses a mode control signal and the ECS generating an active command (See paragraph 0050). - the ECS control module being configured to: receive a mode control signal, and generate an ECS command signal based on the mode control signal;
Song discloses the command generation circuit generating internal commands (See paragraph 0047). - the command generation module being configured to generate an internal command signal based on the ECS command signal, the internal command signal being configured to perform a corresponding ECS operation;
Song discloses an address counter that sequential increases a binary number for the address (See paragraph 0048). Song discloses an END command generated when the count signal reaches a target value (See paragraph 0070). - the address counting module being configured to: perform address counting based on the internal command signal, and generate a counting end signal when counting is completed for a target address; and
Song discloses the error log storage storing the number of errors after the ECS operations are performed (See paragraph 0040). - the error tracking and recording module being configured to: receive an error signal, and generate an error tracking signal based on the counting end signal and the error signal, the error tracking signal being configured to record error information of the ECS operation.
Referring to claim 18, Song discloses performing ECS operations on the semiconductor device with the ECS circuit (See paragraph 0005). - An ECS method, applied to the ECS circuit according to claim 1, and comprising:
Song discloses an ECS mode signal and generating ECS active command in response (See paragraph 0050). - receiving, by the ECS control module, a mode control signal, and generating an ECS command signal based on the mode control signal;
Song discloses the command generation circuit generating internal commands (See paragraph 0047). - receiving, by the command generation module, the ECS command signal, and generating an internal command signal based on the ECS command signal, the internal command signal being configured to perform a corresponding ECS operation;
Song discloses an address counter that sequential increases a binary number for the address (See paragraph 0048). Song discloses an END command generated when the count signal reaches a target value (See paragraph 0070). - receiving, by the address counting module, the internal command signal, performing address counting based on the internal command signal, and generating a counting end signal when counting is completed for a target address; and
Song discloses the error log storage storing the number of errors after the ECS operations are performed (See paragraph 0040). - receiving, by the error tracking and recording module, the counting end signal and an error signal, and generating an error tracking signal based on the counting end signal and the error signal, the error tracking signal being configured to record error information of the ECS operation.
Referring to claim 19, Song discloses a semiconductor system that includes a memory bank and the ECS circuit (See Fig. 1; paragraph 0037). - and A memory, comprising the ECS circuit according to claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Lee et al., U.S. Patent App. Pub. 2022/0068363, hereinafter referred to as “Lee”.
Referring to claim 2, Song discloses all the limitations (See rejection of claim 1) except for The ECS circuit according to claim 1, wherein the mode control signal comprises a multi-purpose command MPC signal or a refresh command signal; and the ECS control module is further configured to: generate the ECS command signal based on the MPC signal when the ECS operation is in a manual ECS operation mode; or generate the ECS command signal based on the refresh command signal when the ECS operation is in an automatic ECS operation mode. However, Song does disclose a refresh command (See Song, paragraph 0005).
Lee discloses memory with ECS mode (See Lee, paragraph 0026). Lee discloses a manual mode for ECS via multipurpose command (see Lee, paragraph 0062). Lee discloses an automatic mode for ECS using a REF command (See Lee, paragraph 0062).
It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to combine the ECS circuit of Song with the manual and automatic ECS mode of Lee. This would have been obvious to do because it allows for multiple ECS mode operations to be undertaken without a corresponding penalty to the refresh rate of the refresh operation (See Lee, paragraph 0026).
Allowable Subject Matter
Claims 3-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Concerning claim 3, the prior art does not disclose “generate an ECS flag signal; and the command control module being configured to: receive the ECS flag signal, obtain the refresh command signal when the ECS flag signal is in a valid state, and generate the ECS command signal based on the refresh command signal.”. Claims 4-6 depend on claim 3 either directly or indirectly and thus are also objected to.
Concerning claim 7, the prior art does not disclose “he internal command generation module being configured to successively generate an active signal, a read command signal, a write command signal, and a precharge signal based on a preset timing condition after the ECS command signal is received; the second timing module being configured to: control a time interval between the active signal and the read command signal to meet a first timing condition, control a time interval between the read command signal and the write command signal to meet a second timing condition, and control a time interval between the write command signal and the precharge signal to meet a third timing condition;” Claims 8-17 depend on claim 7 either directly or indirectly and thus are also objected to.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent App. Pub. 2025/0307047 to Utesheva et al.
- Memory with enhanced fail tracking and scrub fail tracking
U.S. Patent App. Pub. 2025/0117288 to Song
- Semiconductor performing error scrub operation
U.S. Patent App. Pub. 2024/0211344 to Bains et al.
- Adaptive internal error scrubbing and error handling
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/JOSEPH D MANOSKEY/Primary Examiner, Art Unit 2113 December 9, 2025