DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-11 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US Pub. No. 2019/0140652) in view of Katsuragi (US Patent No. 10,333,530)
a) regarding claim 1:
Tsai et al. discloses a voltage-controlled oscillator (Figure 2), comprising:
an input circuit (M0, MI and RI), configured to generate an input current (IIN) according to an input voltage (VIN);
a first current supply circuit (M1), configured to generate a first output current (I1) according to the input current (IIN);
a second current supply circuit (M2), configured to generate a second output current (I2) according to the input current (IIN);
a filtering circuit (140), coupled to the input circuit (M0, MI and RI) and the second current supply circuit (M2), and configured to reduce an influence caused by a variation of the input current on the second current supply circuit (paragraph [0018]); and
an oscillating circuit (150), configured to generate an output clock according to the first output current and the second output current (paragraph [0019]).
Tsai et al. fails to explicitly disclose an input circuit, comprising: an operational amplifier, configured to generate an output voltage according to an input voltage and a feedback voltage; and a first input transistor, configured to generate an input current according to the output voltage and a power supply voltage.
Katsuragi in the same field of endeavor teaches (Figure 9) an input circuit (1418, PT1 and R5) comprising: an operational amplifier (1418), configured to generate an output voltage (VI1) according to an input voltage (VLPF) and a feedback voltage; and a first input transistor (PT1), configured to generate an input current (I1) according to the output voltage (VI1) and a power supply voltage (VDD).
It would have been obvious to one of ordinary skill in the art at the time of the invention to replace the input circuit disclosed by Tsai et al. (i.e. voltage-current conversion circuit having transistor and resistor) with the input circuit taught by Katsuragi (i.e. voltage-current conversion circuit having an operational amplifier) in order to reduce noise (Katsuragi, column 8, lines 36-44 and column 9, lines 12-29) and since it only requires the use of known technique to improve similar devices in the same way.
b) regarding claim 2:
The combination of Tsai et al. and Katsuragi disclose the voltage-controlled oscillator of claim 1, wherein the second output current (Tsai, I2) is larger than the first output current (Tsai, I1 and paragraph [0018]).
c) regarding claim 3:
The combination of Tsai et al. and Katsuragi disclose the voltage-controlled oscillator of claim 1, wherein a ratio of the second output current (Tsai, I2) to the first output current (Tsai, I1) is a value ranging from 10 to 40 (Tsai, paragraph [0018]).
d) regarding claim 4:
The combination of Tsai et al. and Katsuragi disclose the voltage-controlled oscillator of claim 1, wherein the first input transistor (Katsuragi, PT1) comprises:
a high voltage terminal (source), configured to receive the power supply voltage (Katsuragi, VDD);
a control terminal (gate), configured to receive the output voltage (Katsuragi, VI1); and
a low voltage terminal (drain), configured to output the input current (Katsuragi, I1).
e) regarding claim 5:
The combination of Tsai et al. and Katsuragi disclose the voltage-controlled oscillator of claim 1, wherein the operational amplifier (Katsuragi, 1418) comprises:
an inverting terminal (-), configured to receive the input voltage (Katsuragi, VLPF);
a non-inverting terminal (+), coupled to a low voltage terminal of the first input transistor (Katsuragi, PT1), and configured to receive the feedback voltage; and
an output terminal, coupled to a control terminal of the first input transistor (Katsuragi, PT1), and configured to output the output voltage (Katsuragi, VI1).
f) regarding claim 6:
The combination of Tsai et al. and Katsuragi disclose the voltage-controlled oscillator of claim 1, wherein an output terminal of the operational amplifier (Katsuragi, 1418) is coupled to the second current supply circuit (Tsai, M2) through the filtering circuit (Tsai, 140).
g) regarding claim 8:
The combination of Tsai et al. and Katsuragi disclose the voltage-controlled oscillator of claim 1, wherein the first current supply circuit (Tsai, M1) comprises:
a first output transistor (Tsai, M1), comprising:
a high voltage terminal (source), configured to receive the power supply voltage (Tsai, VDD);
a control terminal (gate), coupled to an output terminal of the operational amplifier (Katsuragi, 1418), and configured to receive the output voltage (Katsuragi, VI1); and
a low voltage terminal (drain), configured to generate the first output current (Tsai, I1).
h) regarding claim 9:
The combination of Tsai et al. and Katsuragi disclose the voltage-controlled oscillator of claim 8, wherein the second current supply circuit (Tsai, M2) comprises:
a second output transistor (Tsai, M2), comprising:
a high voltage terminal (source), configured to receive the power supply voltage;
a control terminal (gate), coupled to the output terminal of the operational amplifier (Katsuragi, 1418) through the filtering circuit (Tsai, 140), and configured to receive the output voltage (Katsuragi, VI1); and
a low voltage terminal (drain), configured to generate the second output current (Tsai, I2).
i) regarding claim 10:
The combination of Tsai et al. and Katsuragi disclose the voltage-controlled oscillator of claim 9, wherein the filtering circuit (Tsai, 140) comprises:
a capacitor (Tsai, CLPF), configured to receive the power supply voltage (Tsai, VDD); and
a resistor (Tsai, RLPF), coupled to the output terminal of the operational amplifier (Katsuragi, 1418) and the control terminal of the second output transistor (Tsai, M2).
j) regarding claim 11:
The combination of Tsai et al. and Katsuragi disclose the voltage-controlled oscillator of claim 10, wherein the resistor (Tsai, RLPF) comprises:
a first terminal, coupled to the output terminal of the operational amplifier (Katsuragi, 1418); and
a second terminal, coupled to the capacitor (Tsai, CLPF) and the control terminal of the second output transistor (Tsai, M2).
k) regarding claim 19:
Tsai et al. discloses a phase-locked loop (Figure 6), comprising:
a phase-frequency detector (610), configured to detect a difference between a reference clock (ClkREF) and a feedback clock (ClkFEEDBACK) to output a detection signal;
a charge pump (620), configured to generate a charging/discharging signal according to the detection signal;
a first filtering circuit (630), configured to determine an input voltage according to the charging/discharging signal;
a voltage-controlled oscillator (640 and Figure 2), comprising:
an input circuit (M0, MI and RI), configured to generate an input current (IIN) according to an input voltage (VIN);
a first current supply circuit (M1), configured to generate a first output current (I1) according to the input current (IIN);
a second current supply circuit (M2), configured to generate a second output current (I2) according to the input current (IIN);
a second filtering circuit (140), coupled to the input circuit (M0, MI and RI) and the second current supply circuit (M2), and configured to reduce an influence caused by a variation of the input current on the second current supply circuit (paragraph [0018]); and
an oscillating circuit (150), configured to generate an output clock according to the first output current and the second output current (paragraph [0019]); and
a loop divider (650), configured to generate the feedback clock (ClkFEEDBACK) according to the output clock,
wherein a ratio of a filter bandwidth of the second filtering circuit to a loop bandwidth of the phase-locked loop is not larger than 0.01 (paragraph [0023]).
Tsai fails to explicitly disclose an input circuit, comprising: an operational amplifier, configured to generate an output voltage according to the input voltage and a feedback voltage; and a first input transistor, configured to generate an input current according to the output voltage and a power supply voltage.
Katsuragi in the same field of endeavor teaches (Figure 9) an input circuit (1418, PT1 and R5) comprising: an operational amplifier (1418), configured to generate an output voltage (VI1) according to an input voltage (VLPF) and a feedback voltage; and a first input transistor (PT1), configured to generate an input current (I1) according to the output voltage (VI1) and a power supply voltage (VDD).
It would have been obvious to one of ordinary skill in the art at the time of the invention to replace the input circuit disclosed by Tsai et al. (i.e. voltage-current conversion circuit having transistor and resistor) with the input circuit taught by Katsuragi (i.e. voltage-current conversion circuit having an operational amplifier) in order to reduce noise (Katsuragi, column 8, lines 36-44 and column 9, lines 12-29) and since it only requires the use of known technique to improve similar devices in the same way.
l) regarding claim 20:
The combination of Tsai et al. and Katsuragi disclose the phase-locked loop of claim 19, wherein the second output current (Tsai, I2) is larger than the first output current (Tsai, I1 and paragraph [0018]).
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Tsai et al. and Katsuragi as applied to claim1 above, and further in view of Raghunathan et al. (US Pub. No. 2012/0256693).
a) regarding claim 7:
The combination of Tsai et al. and Katsuragi disclose the voltage-controlled oscillator of claim 1.
The combination of Tsai et al. and Katsuragi fails to explicitly disclose wherein the input circuit further comprises: a second input transistor, comprising: a high voltage terminal, coupled to a low voltage terminal of the first input transistor and a non-inverting terminal of the operational amplifier; a control terminal, coupled to the high voltage terminal of the second input transistor; and a low voltage terminal, coupled to a low potential terminal.
Raghunathan et al. in the same field of endeavor teaches (Figure 3) wherein an input circuit (10, 11 and 25) comprises: a second input transistor (27), comprising: a high voltage terminal (source), coupled to a low voltage terminal of a first input transistor (11) and a non-inverting terminal of an operational amplifier (10); a control terminal (gate), coupled to the high voltage terminal of the second input transistor (27); and a low voltage terminal (drain), coupled to a low potential terminal (ground).
It would have been obvious to one of ordinary skill in the art at the time of the invention to replace the resistor in the input circuit disclosed by the combination of Tsai et al. and Katsuragi with a replica of an oscillator as taught by Raghunathan et al. since it only requires simple substitution of one known element for another to obtain predictable results.
Allowable Subject Matter
Claims 12-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to disclose or make obvious wherein the input circuit further comprises: a third input transistor, configured to generate a mirror current according to the input current, along with all the other limitations as required by claim 12.
Conclusion
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/PATRICK O NEILL/ Primary Examiner, Art Unit 2842